/* Copyright 1991-1992 Wind River Systems, Inc. */	.data	.globl	_copyright_wind_river	.long	_copyright_wind_river/*modification history--------------------01f,04jun96,ms   fixed SPR 6583 - tracing during fpp emulation trashes a001e,23aug92,jcf  changed bxxx to jxx.01d,26may92,rrr  the tree shuffle01c,17dec91,kdl  added changes from Motorola "skeleton.sa" v3.2:		 don't do fsave unless frame format id is 40.01b,04dec91,kdl  fixed register saving in __x_fpsp_ill_inst.01a,12aug91,jcf  adapted from Motorola version 2.1.*//*DESCRIPTIONskeleton.s 3.1 12/10/90,  2.1 Motorola 040 Floating Point Software PackageThe exception handler entry points for the FPSP are as follows:    ill_inst	-> __x_fpsp_ill_inst    fline	-> __x_fpsp_fline    bsun	-> __x_fpsp_bsun    inex	-> __x_fpsp_inex    dz		-> __x_fpsp_dz    unfl	-> __x_fpsp_unfl    operr	-> __x_fpsp_operr    ovfl	-> __x_fpsp_ovfl    snan	-> __x_fpsp_snan    unsupp	-> __x_fpsp_unsuppIf the FPSP determines that the exception is one that must be handled bythe operating system then there will be a return from the package by a 'jmpreal_xxxx' where xxxx corresponds to an exception outlined above.  At thatpoint the machine state will be identical to the state before the FPSP wasentered.  In particular, whatever condition that caused the exception willstill be pending when the FPSP package returns.  This will enable systemspecific code, contained in excALib()/excLib() to handle the exception.If the exception was completely handled by the package, then the returnwill be via a 'jmp fpsp_done'.  Unless there is OS specific work to be done(such as handling a context switch or interrupt) the user program can beresumed via 'rte'.In the following skeleton code, some typical 'real_xxxx' handling code isshown.  This code may need to be moved to an appropriate place in thetarget system, or rewritten.Copyright (C) Motorola, Inc. 1990All Rights ReservedTHIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLAThe copyright notice above does not evidence anyactual or intended publication of such source code.Original VxWorks implementation by Jim Foris, GE Medical Systems.NOMANUAL*/#include "fpsp040E.h"/* imports */	.globl	_excStub	.globl	__x_b1238_fix	.globl	__x_do_func	.globl	__x_gen_except	.globl	__x_get_op	.globl	__x_sto_res/* globals */	.globl	__x_real_bsun	/* called from __x_fpsp_bsun for OS handling */	.globl	__x_real_dz	/* called from __x_fpsp_dz for OS handling */	.globl	__x_real_operr	/* called from __x_fpsp_operr for OS handling */	.globl	__x_real_ovfl	/* called from __x_fpsp_ovfl for OS handling */	.globl	__x_real_snan	/* called from __x_fpsp_snan for OS handling */	.globl	__x_real_trace	/* called from __x_fpsp_trace for OS handling */	.globl	__x_real_unfl	/* called from __x_fpsp_unfl for OS handling */	.globl	__x_real_unsupp	/* called from __x_fpsp_unsupp for OS handling*/	.globl	__x_real_inex	/* called from __x_fpsp_inex for OS handling */	.globl	__x_fpsp_dz	/* divide by zero exception handler */	.globl	__x_fpsp_inex	/* inexact exception handler */	.globl	__x_fpsp_fline	/* fline exception handler */	.globl	__x_fpsp_ill_inst  /* illegal instruction exception handler */	.globl	__x_fpsp_fmt_error /* called if format not supported */	.globl	__x_fpsp_done	/* called from handlers to return to user */	.globl	__x_mem_read	/* utility routine to read memory */	.globl	__x_mem_write	/* utility routine to write memory */	.text/********************************************************************************* BSUN exception** This sample handler simply clears the nan bit in the FPSR.*/__x_real_bsun:	link		a6,#-192	fsave		a7@-	bclr		#E1,a6@(E_BYTE)	/* bsun is always an E1 exception */	fmovel		FPSR,a7@-	bclr		#nan_bit,a7@	fmovel		a7@+,FPSR	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Divide by Zero exception**/__x_fpsp_dz:__x_real_dz:	link		a6,#-192	fsave		a7@-	bclr		#E1,a6@(E_BYTE)	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Operand Error exception*/__x_real_operr:	link		a6,#-192	fsave		a7@-	bclr		#E1,a6@(E_BYTE)	/* operr is always an E1 exception */	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Overflow exception*/__x_real_ovfl:	link		a6,#-192	fsave		a7@-	bclr		#E3,a6@(E_BYTE)	/* clear and test E3 flag */	jne 		ovfl_done	bclr		#E1,a6@(E_BYTE)ovfl_done:	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Signalling NAN exception*/__x_real_snan:	link		a6,#-192	fsave		a7@-	bclr		#E1,a6@(E_BYTE)	/* snan is always an E1 exception */	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Trace Exception*/__x_real_trace:	movel		a0, sp@-	/* save a0 to the stack */	movec		vbr,a0		/* compute IV_TRACE vector address */	movel		a0@(0x24),a0	movel		a0, sp@-	/* and push it on the stack */	movel		sp@(0x4), a0	/* restore a0 */	rtd		#4		/* jump to trace vector *//********************************************************************************* Underflow exception*/__x_real_unfl:	link		a6,#-192	fsave		a7@-	bclr		#E3,a6@(E_BYTE)	/* clear and test E3 flag */	jne 		unfl_done	bclr		#E1,a6@(E_BYTE)unfl_done:	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Unsupported data type exception*/__x_real_unsupp:	link		a6,#-192	fsave		a7@-	bclr		#E1,a6@(E_BYTE)	/* unsupp is always an E1 exception */	frestore	a7@+	unlk		a6	jmp		_excStub	/* start VxWorks exception handling *//********************************************************************************* Inexact exception** All inexact exceptions are real, but the 'real' handler* will probably want to clear the pending exception.* The provided code will clear the E3 exception (if pending),* otherwise clear the E1 exception.  The frestore is not really* necessary for E1 exceptions.** Code following the 'inex' label is to handle bug #1232.  In this* bug, if an E1 snan, ovfl, or unfl occured, and the process was* swapped out before taking the exception, the exception taken on* return was inex, rather than the correct exception.  The snan, ovfl,* and unfl exception to be taken must not have been enabled.  The* fix is to check for E1, and the existence of one of snan, ovfl,* or unfl bits set in the fpsr.  If any of these are set, branch* to the appropriate  handler for the exception in the fpsr.  Note* that this fix is only for d43b parts, and is skipped if the* version number is not 0x40.*/__x_fpsp_inex:	link		a6,#-LOCAL_SIZE	fsave		a7@-	cmpib		#VER_40,a7@		| test version number	jne 		not_fmt40	fmovel		fpsr,a7@-	btst		#E1,a6@(E_BYTE)		| test for E1 set	jeq 		not_b1232	btst		#__x_snan_bit,a7@(2)	| test for snanbeq		__x_inex_ckofl	addl		#4,sp	frestore	a7@+	unlk		a6	jra		__x_fpsp_snan__x_inex_ckofl:	btst		#__x_ovfl_bit,a7@(2)	| test for ovfl	jeq		__x_inex_ckufl	addl		#4,sp	frestore	a7@+	unlk		a6	jra		__x_fpsp_ovfl__x_inex_ckufl:	btst		#__x_unfl_bit,a7@(2)	| test for unfl	jeq		not_b1232	addl		#4,sp	frestore	a7@+	unlk		a6	jra		__x_fpsp_unfl|| We do not have the bug 1232 case.  Clean up the stack and call| __x_real_inex.|not_b1232:	addl		#4,sp	frestore	a7@+	unlk		a6__x_real_inex:	link		a6,#-LOCAL_SIZE	fsave		a7@-