?? reg78e65.h
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/*--------------------------------------------------------------------------
REG52.H
Header file for generic 80C52 and 80C32 microcontroller.
Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
All rights reserved.
--------------------------------------------------------------------------*/
/* BYTE Registers */
#ifndef Reg52_h
#define Reg52_h
sfr P0 = 0x80;
sfr P1 = 0x90;
sfr P2 = 0xA0;
sfr P3 = 0xB0;
sfr P4 = 0xD8;
sfr PSW = 0xD0;
sfr ACC = 0xE0;
sfr B = 0xF0;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr PCON = 0x87;
sfr TCON = 0x88;
sfr TMOD = 0x89;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr IE = 0xA8;
sfr IP = 0xB8;
sfr SCON = 0x98;
sfr SBUF = 0x99;
/* 8052 Extensions */
sfr T2CON = 0xC8;
sfr RCAP2L = 0xCA;
sfr RCAP2H = 0xCB;
sfr TL2 = 0xCC;
sfr TH2 = 0xCD;
/* BIT Registers */
/* PSW */
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit P = PSW^0; //8052 only
/* TCON */
sbit TF1 = TCON^7;
sbit TR1 = TCON^6;
sbit TF0 = TCON^5;
sbit TR0 = TCON^4;
sbit IE1 = TCON^3;
sbit IT1 = TCON^2;
sbit IE0 = TCON^1;
sbit IT0 = TCON^0;
/* IE */
sbit EA = IE^7;
sbit ET2 = IE^5; //8052 only
sbit ES = IE^4;
sbit ET1 = IE^3;
sbit EX1 = IE^2;
sbit ET0 = IE^1;
sbit EX0 = IE^0;
/* IP */
sbit PT2 = IP^5;
sbit PS = IP^4;
sbit PT1 = IP^3;
sbit PX1 = IP^2;
sbit PT0 = IP^1;
sbit PX0 = IP^0;
/* P3 */
sbit RD = P3^7;
sbit WR = P3^6;
sbit T1 = P3^5;
sbit T0 = P3^4;
sbit INT1 = P3^3;
sbit INT0 = P3^2;
sbit TXD = P3^1;
sbit RXD = P3^0;
/* SCON */
sbit SM0 = SCON^7;
sbit SM1 = SCON^6;
sbit SM2 = SCON^5;
sbit REN = SCON^4;
sbit TB8 = SCON^3;
sbit RB8 = SCON^2;
sbit TI = SCON^1;
sbit RI = SCON^0;
/* P1 */
sbit T2EX = P1^1; // 8052 only
sbit T2 = P1^0; // 8052 only
/* T2CON */
sbit TF2 = T2CON^7;
sbit EXF2 = T2CON^6;
sbit RCLK = T2CON^5;
sbit TCLK = T2CON^4;
sbit EXEN2 = T2CON^3;
sbit TR2 = T2CON^2;
sbit C_T2 = T2CON^1;
sbit CP_RL2 = T2CON^0;
sbit P0_0 = P0^0;
sbit P0_1 = P0^1;
sbit P0_2 = P0^2;
sbit P0_3 = P0^3;
sbit P0_4 = P0^4;
sbit P0_5 = P0^5;
sbit P0_6 = P0^6;
sbit P0_7 = P0^7;
sbit P1_0 = P1^0;
sbit P1_1 = P1^1;
sbit P1_2 = P1^2;
sbit P1_3 = P1^3;
sbit P1_4 = P1^4;
sbit P1_5 = P1^5;
sbit P1_6 = P1^6;
sbit P1_7 = P1^7;
sbit P2_0 = P2^0;
sbit P2_1 = P2^1;
sbit P2_2 = P2^2;
sbit P2_3 = P2^3;
sbit P2_4 = P2^4;
sbit P2_5 = P2^5;
sbit P2_6 = P2^6;
sbit P2_7 = P2^7;
sbit P3_0 = P3^0;
sbit P3_1 = P3^1;
sbit P3_2 = P3^2;
sbit P3_3 = P3^3;
sbit P3_4 = P3^4;
sbit P3_5 = P3^5;
sbit P3_6 = P3^6;
sbit P3_7 = P3^7;
sbit P4_0 = P4 ^ 0;
sbit P4_1 = P4 ^ 1;
sbit P4_2 = P4 ^ 2;
sbit P4_3 = P4 ^ 3;
// For Winbond MCU
#ifdef W78e532
sfr TA=0xc7;
sfr CHPCON=0x9f; //jr add for w78e532
sfr SFRCN=0xaf;
sfr ROMCON=0xab;
#else
sfr CHPENR = 0xF6;//for Winbond Mcu to the Isp mode
sfr CHPCON = 0xBF;//for Winbond Mcu to the Isp mode
#endif
// for Myson MTV312
#if 0// for Myson 312MV//vick myson
#define XFR_ADDR 0xF00
#define XFR_DDC 0xE00
#define DDCRAM (((BYTE xdata*)XFR_DDC)[0x00])
#define IICCTR (((BYTE xdata*)XFR_ADDR)[0x00])
#define IICSTUSL (((BYTE xdata*)XFR_ADDR)[0x01])
#define IICSTUSH (((BYTE xdata*)XFR_ADDR)[0x02])
#define INTFLG (((BYTE xdata*)XFR_ADDR)[0x03])
#define INTEN (((BYTE xdata*)XFR_ADDR)[0x04])
#define MBUF (((BYTE xdata*)XFR_ADDR)[0x05])
#define RCATXABUF (((BYTE xdata*)XFR_ADDR)[0x06])
#define DDCCTR (((BYTE xdata*)XFR_ADDR)[0x06])
#define SLVAADDR (((BYTE xdata*)XFR_ADDR)[0x07])
#define SLVAADR (((BYTE xdata*)XFR_ADDR)[0x07])
#define RCBTXBBUF (((BYTE xdata*)XFR_ADDR)[0x08])
#define SLVBADDR (((BYTE xdata*)XFR_ADDR)[0x09])
#define DBUF (((BYTE xdata*)XFR_ADDR)[0x0A])
#define ISPSLV (((BYTE xdata*)XFR_ADDR)[0x0B])
#define ISPEN (((BYTE xdata*)XFR_ADDR)[0x0C])
#define MADC (((BYTE xdata*)XFR_ADDR)[0x10])
#define DA0 (((BYTE xdata*)XFR_ADDR)[0x20])
#define DA1 (((BYTE xdata*)XFR_ADDR)[0x21])
#define DA2 (((BYTE xdata*)XFR_ADDR)[0x22])
#define DA3 (((BYTE xdata*)XFR_ADDR)[0x23])
#define DA4 (((BYTE xdata*)XFR_ADDR)[0x24])
#define DA5 (((BYTE xdata*)XFR_ADDR)[0x25])
#define DA6 (((BYTE xdata*)XFR_ADDR)[0x26])
#define DA7 (((BYTE xdata*)XFR_ADDR)[0x27])
#define DA8 (((BYTE xdata*)XFR_ADDR)[0x28])
#define DA9 (((BYTE xdata*)XFR_ADDR)[0x29])
#define DA10 (((BYTE xdata*)XFR_ADDR)[0x2A])
#define DA11 (((BYTE xdata*)XFR_ADDR)[0x2B])
#define DA12 (((BYTE xdata*)XFR_ADDR)[0x2C])
#define DA13 (((BYTE xdata*)XFR_ADDR)[0x2D])
#define PADMOD0 (((BYTE xdata*)XFR_ADDR)[0x50])
#define PADMOD1 (((BYTE xdata*)XFR_ADDR)[0x51])
#define PADMOD2 (((BYTE xdata*)XFR_ADDR)[0x52])
#define PADMOD3 (((BYTE xdata*)XFR_ADDR)[0x53])
#define PADMOD4 (((BYTE xdata*)XFR_ADDR)[0x54])
#define PADMOD5 (((BYTE xdata*)XFR_ADDR)[0x55])
#define OPTION (((BYTE xdata*)XFR_ADDR)[0x56])
#define XBANK (((BYTE xdata*)XFR_ADDR)[0x35])
#define P4_0 (((BYTE xdata*)XFR_ADDR)[0x58])
#define P4_1 (((BYTE xdata*)XFR_ADDR)[0x59])
#define P4_2 (((BYTE xdata*)XFR_ADDR)[0x5A])
#define P5_0 (((BYTE xdata*)XFR_ADDR)[0x30])
#define P5_1 (((BYTE xdata*)XFR_ADDR)[0x31])
#define P5_2 (((BYTE xdata*)XFR_ADDR)[0x32])
#define P5_3 (((BYTE xdata*)XFR_ADDR)[0x33])
#define P5_4 (((BYTE xdata*)XFR_ADDR)[0x34])
#define P5_5 (((BYTE xdata*)XFR_ADDR)[0x35])
#define P5_6 (((BYTE xdata*)XFR_ADDR)[0x36])
#define P6_0 (((BYTE xdata*)XFR_ADDR)[0x38])
#define P6_1 (((BYTE xdata*)XFR_ADDR)[0x39])
#define P6_2 (((BYTE xdata*)XFR_ADDR)[0x3A])
#define P6_3 (((BYTE xdata*)XFR_ADDR)[0x3B])
#define P6_4 (((BYTE xdata*)XFR_ADDR)[0x3C])
#define P6_5 (((BYTE xdata*)XFR_ADDR)[0x3D])
#define P6_6 (((BYTE xdata*)XFR_ADDR)[0x3E])
#define P6_7 (((BYTE xdata*)XFR_ADDR)[0x3F])
#define HVSTUS (((BYTE xdata*)XFR_ADDR)[0x40])
#define HCNTH (((BYTE xdata*)XFR_ADDR)[0x41])
#define HCNTL (((BYTE xdata*)XFR_ADDR)[0x42])
#define VCNTH (((BYTE xdata*)XFR_ADDR)[0x43])
#define VCNTL (((BYTE xdata*)XFR_ADDR)[0x44])
#define HVCTR0 (((BYTE xdata*)XFR_ADDR)[0x40])
#define HVCTR2 (((BYTE xdata*)XFR_ADDR)[0x42])
#define HVCTR3 (((BYTE xdata*)XFR_ADDR)[0x43])
#define HVINTFLG (((BYTE xdata*)XFR_ADDR)[0x48])
#define HVINTEN (((BYTE xdata*)XFR_ADDR)[0x49])
// #define P4OUT (((BYTE xdata*)XFR_ADDR)[0x44]) // for MYSON 112
// #define SLVCTR (((BYTE xdata*)XFR_ADDR)[0x90]) // for MYSON 112
// #define WDT (((BYTE xdata*)XFR_ADDR)[0x80]) // for MYSON 112
#define WDT (((BYTE xdata*)XFR_ADDR)[0x18]) // for MYSON 112
#endif
#endif
//***************************************************************
//Port define
//***************************************************************
/*sbit Mute_Port=P0^0;
sbit OSD_CL=P0^1;
sbit OSD_DI=P0^2;
sbit SyncDetPort=P0^3;
sbit OSD_CE=P0^4;
sbit DVD_Rst_Port=P0^5;
sbit ANT_X=P0^6;
sbit Stable=P0^7;
sbit Hsync = P1^0;
sbit Vsync = P1^0;//P1^1;
sbit Power_Port=P1^2;
sbit SCL=P1^3; //模擬I2C時鐘控制位//
sbit SDA=P1^4; //模擬I2C數據傳送位//
sbit SW1=P1^5;
sbit SW2=P1^6;
sbit DVD_Save_Port=P1^7;
sbit Mode_key=P2^0;
sbit Ch_dec_key=P2^1;
sbit Play_key=P2^2;
sbit Power_key=P2^3;
sbit audio_test=P2^4;
sbit dsa_ack = P2^5;
sbit dsa_stb = P2^6;
sbit dsa_data = P2^7;
sbit swa_test = P3^0;
sbit swb_test = P3^1;
sbit acc_test = P3^3;
sbit eject_o_ctrl= P3^4;
sbit eject_i_ctrl= P3^5;
sbit Ch_inc_key=P3^6;
sbit insw_test = P3^7;
sbit tv_ctrl = P4^0;
//bit DVD_LED;
//bit TV_LED;
//bit AV_LED;
//bit Power_LED; */
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