create_project FPGAcreate_library systemcreate_library pex_libcreate_library armadd_file -library system -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/xilinx_pkg.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe_pkg.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/systolic_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/lad_bus_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/led_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mem_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe0_bus_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/clock_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/clock_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/io_conn_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/lad_bus_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/led_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mem_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe0_bus_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/systolic_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe_mezz_mem_pkg.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pex_mezz_mem_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pex_mezz_mem_io_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe_lad2mem_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pe_arm2mem_if_entarch.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pex_ent.vhdadd_file -library pex_lib -format VHDL F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pex_synth.vhdadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/shifter.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/alu.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/arm9.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/comp42_2.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/comp42_n40.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/comp42_n64.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/control.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/counters.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/dcache.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/decode.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/dtag_synth.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/icache.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/id.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/ifetch.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/interlock.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/itag_synth.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mapreg.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mapspsr.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/me.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/miniram.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mmu_new.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/mult.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/multacc.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pardef.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/ppselect.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/ram1p_synth.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/ram2p_synth.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/regfile.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/align.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/pipe.vadd_file -library arm -format Verilog F:/arm/isc/hardware/ARM10/behavioral/pipelined/fpga2/ex.vanalyze_file -progresscreate_chip -progress -name PEX -target VIRTEX -device V1000BG560 -speed -6 -frequency 5 -module -area_only -quick_mode PEXcurrent_chip PEXoptimize_chip -name PEX-Optimized -progressexport_chip -dir D:\kohler\FPGAlist_message