cmpm	*(numTxPkts),#0			; check if DMA is disabled (no packets to transmit)
	bc	NoAdjust2,ntc			; if DMA still on, nothing to worry about, so skip out
	xorm	#1,*(txbufhalf)			; set txbufhalf to 0 to point to 1st half	
	stm	#TxDMAptr,DMSA			; set subaddress to Tx DMA Source register.
	stm	#Tx1stStart,DMSDN		; Set Tx DMA pointer to start of 1st half
NoAdjust2:
 .endif		; end 5402 workaround
	bitf	*(txbufhalf),#1                	; check if in 2nd half of buffer
	xorm	#1,*(txbufhalf)        		; toggle the buffer half which is available
	stm	#Tx2ndStart,ar2			; assume in 2nd half of buffer (point to start of this half) 
	xc	2,ntc                		; if not,  
	  stm	#Tx1stStart,ar2  		; point ar2 to the start of first half of buffer
	xc	2,aneq   			; if sending break (a!=0)
	  ld	#0xffff,a			; init a to all 1's   
	cmpl	a				; a=a_ (if input is 0, send all 1's, else send all 0's)	  
	rpt	#TxPKTBITS-1    		; create packet of all 0 or all 1
	  stl	a,*ar2fwd                      
        b	startTx				; branch into TxChar routine to start the transmission


********* PRIVATE ROUTINES ***********	
 .if (PARITY==EVEN)|(PARITY==ODD)
*****************************************************************
*	Function: ParityCalc					*
*	Purpose: Determines the parity of an input word		*
*		 using a successive approximation scheme.	*
*		 The number of iterations is determined		*
*		 at assembly time by the number of bits		*
*		 in each character.				*
*	Inputs:	 al = character to determine parity of.		*
*	Outputs: tc = 0 - parity is even			*
*		 tc = 1 - parity is odd				*
*	Modified: ag,ah,st0(tc)					*
***************************************************************** 
ParityCalc: 
	pshm	al				; save character	
   .if DATABITS+PARITYBITS>16            	;
	xor	a,16,a                          ;
   .endif                                  	;
   .if DATABITS+PARITYBITS>8             	;
	xor	a,8,a                           ;
   .endif                                  	;
   .if DATABITS+PARITYBITS>4             	;
	xor	a,4,a                           ;
   .endif                                  	;
   .if DATABITS+PARITYBITS>2             	;
	xor	a,2,a                           ;
   .endif                                  	;
   .if DATABITS+PARITYBITS>1             	;
	xor 	a,1,a                           ;
   .endif	                                ;                                  
	bitf	*(al),#PARITYCHECK		; test the calculated parity and return it in TC
	popm	al				; restore character
	ret            
 .endif
 .if PARITY!=NO
*****************************************************************
*	Function: ParityCheck					*
*	Purpose: Computes parity of input word and determines	*
*		 if it is valid, according to settings.		*
*		 The parity setting is made at assembly time.	*
*		 The input is assumed to only contain data and	*
*		 parity bits.  No start or stop bits should	*
*		 be in the word.				*
*	Inputs:	 al = character to check parity of.  Must	*
*		 only contain data and parity bits.		*
*		 DP = UARTvars (uses data-page direct 		*
*		      addressing)				*
*	Outputs: al = character with parity bit stripped.	*
*		 _UARTLSR - if parity is invalid, Parity	*
*		 Error bit is set in _UARTLSR.			*
*	Modified: ah,ag,_UARTLSR,st0(tc)			*
***************************************************************** 	
ParityCheck: 
   .if (PARITY==EVEN)|(PARITY==ODD)
	call	ParityCalc                      ; find parity of received word (output tc==0-even, tc==1-odd)
   .else ; (PARITY==MARK)|(PARITY==SPACE)
	bitf	*(al),#(1<<DATABITS)		; test the parity bit (tc==0-space, tc==1-mark)
   .endif
	and	#(1<<DATABITS)-1,a		; mask out the parity bit (char was returned in AL)
   .if (PARITY==EVEN)|(PARITY==SPACE)     
   	xc	2,tc				; if parity is even/space skip error report
   .else ; (PARITY==ODD)|(PARITY==MARK)	
	xc	2,ntc				; if parity is odd/mark skip error report
   .endif                               
	  orm	#PE,@_UARTLSR			; set Parity Error flag in status register  
	ret	                                ;
 .endif ; if PARITY!=NO

*****************************************************************
*	Table:   McBSPInitTable					*
*	Purpose: Contains all values to initialize the McBSP	*
*		 used by the UART.  Note that the McBSP which	*
*		 will be used is defined at assembly time.	*
*		 Specifically, the following major settings 	*
*		 will be made:					*
*                                               		*
*	Receiver: 						*
*		  - Dual phase frames                       	*
*		    (1st phase = RxPKTBITS-RxHSTOPBITS words of *
*		     16 bits each)				*
*		    (2nd phase = RxHSTOPBITS words of 		*
*		     8 bits each)				*
*		  - Enable frame ignore                     	*
*		  - 1 bit delay between FSR and data		*
*                                                            	*
*	Transmitter:                                         	*
*		  - Dual phase frames  				*
*		    (1st phase = TxPKTBITS-TxHSTOPBITS words of	*
*		     16 bits each)				*
*		    (2nd phase = TxHSTOPBITS words of 		*
*		     8 bits each)				*
*		  - Enable frame ignore                     	*
*		  - 0 bit delay between FSX and data		* 
*		  - Generate CLKG and FSX using baud rate	*
*		    divisor given in assembly-time conditions	*
***************************************************************** 
McBSPInitTable:
	.word	SRGR1                  	; SRGR1 settings:
	.word	0000000000000000b | BAUDRATEDIV   	
; 		00000000~~~~~~~~b		FWID:	unused because FSGM=0
;		~~~~~~~~xxxxxxxxb		CLKGDV:	Sample rate generator clock divider=(BAUDRATEDIV+1)
	.word	SRGR2                  	; SRGR2 settings:
	.word	0010000000000000b
;		0~~~~~~~~~~~~~~~b		GSYNC:	sample rate generator clock (CLKG) is free running
;		~0~~~~~~~~~~~~~~b		CLKSP:	unused
;		~~1~~~~~~~~~~~~~b		CLKSM:	Sample rate generator clock derived from CPU clock
;		~~~0~~~~~~~~~~~~b		FSGM:	Transmit frame sync (FSX) due to DXR-to-XSR copy
;		~~~~000000000000b		FPER:	unused because FSGM=0
	.word	PCR                    	; PCR settings:
	.word	0000101100001100b                  	
;		00~~~~~~~~~~~~~~b		reserved
;		~~0~~~~~~~~~~~~~b		XIOEN:	DR,CLKS not GPI; DX not GPO; FSX,CLKX not GPIO
;		~~~0~~~~~~~~~~~~b		RIOEN:	DR,CLKS not GPI; DX not GPO; FSR,CLKR not GPIO
;		~~~~1~~~~~~~~~~~b		FSXM:	Transmit frame sync determined by FSGM (in SRGR2)
;		~~~~~0~~~~~~~~~~b		FSRM:	Receive frame sync generated by external device (FSR is input)
;		~~~~~~1~~~~~~~~~b		CLKXM:	CLKX is output driven by internal sample rate generator
;		~~~~~~~1~~~~~~~~b		CLKRM:	CLKR is output driven by internal sample rate generator
;		~~~~~~~~0~~~~~~~b		reserved
;		~~~~~~~~~0~~~~~~b		CLKS_STAT: Read Only
;		~~~~~~~~~~0~~~~~b		DX_STAT:Read Only
;		~~~~~~~~~~~0~~~~b		DR_STAT:Read Only
;		~~~~~~~~~~~~1~~~b		FSXP:	FSX is active low
;		~~~~~~~~~~~~~1~~b		FSRP:	FSR is active low
;		~~~~~~~~~~~~~~0~b		CLKXP:	Transmit data sampled on rising edge of CLKX
;		~~~~~~~~~~~~~~~0b		CLKRP:	Receive data sampled on falling edge of CLKR
	.word	SPCR1             	; SPCR1 settings:
	.word	0000000000000000b
;		0~~~~~~~~~~~~~~~b		DLB:	Digital loopback mode is disabled
;		~00~~~~~~~~~~~~~b		RJUST:	Right-justify and zero-fill MSbs in DRR(1/2)
;		~~~00~~~~~~~~~~~b		CLKSTP:	Clock Stop Mode disabled   
;		~~~~~000~~~~~~~~b		reserved
;		~~~~~~~~0~~~~~~~b		DXENA:	DX enabler is off 
;		~~~~~~~~~0~~~~~~b		ABIS: 	A-bis mode is disabled
;		~~~~~~~~~~00~~~~b		RINTM: 	RINT driven by RRDY
;		~~~~~~~~~~~~0~~~b		RSYNCERR: Read Only
;		~~~~~~~~~~~~~0~~b		RFULL: 	Read Only
;		~~~~~~~~~~~~~~0~b		RRDY: 	Read Only
;		~~~~~~~~~~~~~~~0b		RRST_: 	Receiver is disabled and in reset state
	.word	SPCR2			; SPCR2 settings:
	.word	0000000100000000b
;		000000~~~~~~~~~~b		reserved
;		~~~~~~0~~~~~~~~~b		FREE:  	Free running mode is disabled
;		~~~~~~~1~~~~~~~~b		SOFT: 	Soft mode enabled
;		~~~~~~~~0~~~~~~~b		FRST_:	Frame sync generator is reset 
;		~~~~~~~~~0~~~~~~b		GRST_: 	Sample rate generator is pulled out of reset
;		~~~~~~~~~~00~~~~b		XINTM: 	XINT driven by XRDY
;		~~~~~~~~~~~~0~~~b		XSYNCERR: Read Only
;		~~~~~~~~~~~~~0~~b		XEMPTY:	Read Only
;		~~~~~~~~~~~~~~0~b		XRDY: 	Read Only
;		~~~~~~~~~~~~~~~0b		XRST_: 	Transmitter is disabled and in reset state
	.word	RCR1			; RCR1 settings:
	.word	0000000001000000b|(((RxPKTBITS-RxHSTOPBITS) -1) <<8) 
;		0~~~~~~~~~~~~~~~b		reserved
;		~xxxxxxx~~~~~~~~b		RFRLEN1:Receive frame length for phase 1 is RxPKTBITS-RxHSTOPBITS words
;		~~~~~~~~010~~~~~b		RWDLEN1:Receive word length for phase 1 is 16 bits	
;		~~~~~~~~~~~00000b		reserved
	.word	RCR2			; RCR2 settings:
	.word	1000000000000101b|((RxHSTOPBITS -1) <<8)
;		1~~~~~~~~~~~~~~~b		RPHASE:	dual phase receive frame
;		~xxxxxxx~~~~~~~~b		RFRLEN2:Receive frame length for phase 2 is RxHSTOPBITS
;		~~~~~~~~000~~~~~b		RWDLEN2:Receive word length for phase 2 is 8 bits 
;		~~~~~~~~~~~00~~~b		RCOMPAND:no companding, data transfer starts with MSb first
;		~~~~~~~~~~~~~1~~b		RFIG:	ignore receive frame syncs after the first one
;		~~~~~~~~~~~~~~01b		RDATDLY:1-bit delay between FSR and data
	.word	XCR1			; XCR1 settings:
	.word	0000000001000000b|((TxPKTBITS - TxHSTOPBITS-1) <<8)
;		0~~~~~~~~~~~~~~~b		reserved
;		~xxxxxxx~~~~~~~~b		XFRLEN1:Transmit frame length for phase 1 is TxPKTBITS - TxHSTOPBITS words
;		~~~~~~~~010~~~~~b		XWDLEN1:Transmit word length for phase 1 is 16 bits	
;		~~~~~~~~~~~00000b		reserved
	.word	XCR2			; XCR2 settings:
	.word	1000000000000100b|((TxHSTOPBITS - 1) <<8)
;		1~~~~~~~~~~~~~~~b		XPHASE:	dual phase transmit frame
;		~xxxxxxx~~~~~~~~b		XFRLEN2:Transmit frame length for phase 2 is TxHSTOPBITS words
;		~~~~~~~~000~~~~~b		XWDLEN2:Transmit word length for phase 2 is 8 bits 
;		~~~~~~~~~~~00~~~b		XCOMPAND:no companding, data transfer starts with MSb first
;		~~~~~~~~~~~~~1~~b		XFIG:	ignore transmit frame syncs after the first one
;		~~~~~~~~~~~~~~00b		XDATDLY:0-bit delay between FSX and data
EndMcBSPInitTable:
 
*****************************************************************
*	Table:   DMAInitTable					*
*	Purpose: Contains all values to initialize the DMA	*
*		 channels used by the UART.  Note that the	*
*		 DMA channels which are used are defined at	*
*		 assembly-time, as is the McBSP.  Specifically,	*
*		 the following major settings will be made:	*
*                                               		*
*	Rx Channel: 						*
*		- ABU mode (buffer size is RxPKTBITS*2)		* 
*		- Interrupts are at each 1/2 buffer point	*
*		- Source is McBSP DRR1 register			*
*		- Destination is Rx raw data buffer		* 
*		- Synchronized to McBSP Receive Event (REVT)	*
*                                                            	*
*	Tx Channel:                                         	*
*		- ABU mode (buffer size is TxPKTBITS*2)		*
*		- Interrupts are at each 1/2 buffer point	*
*		- Source is Tx raw data buffer			*
*		- Destination is McBSP DXR1 register		*
*		- Synchronized to McBSP Transmit Event (XEVT)	*
*                                                            	*
*****************************************************************  
DMAInitTable:                       	
	.word	RxDMAptr ;;;;;;;;;;;;;;;;;;;;;;;; DMA Rx Channel settings.  Use autoincrement of subaddress after 1st word
DMARxInitTable:
	.word	DRR1reg         		; DMSRC: Source is McBSP DRR1 register 
	.word	Rx1stStart			; DMDST: Destination is Receive raw data buffer
	.word	2*RxPKTBITS			; DMCTR: Element count (words to transfer) is 2*total bits per character
	.word	0000000000000000b|(REVT<<12)	; DMSFC4:
;		xxxx~~~~~~~~~~~~b			DSYN: DMA sync event is one of the McBSP Receive Events
;		~~~~0~~~~~~~~~~~b			DBLW: Single-word mode (each element is 16 bits)
;		~~~~~000~~~~~~~~b			reserved
;		~~~~~~~~00000000b			Frame Count: not relevant in ABU mode	 
	.word   0111000001000001b|(DMAptrMod<<2); DMMCR:
;		0~~~~~~~~~~~~~~~b			AUTOINIT: Auto-initialization is disabled
;		~1~~~~~~~~~~~~~~b			DINM:	Interrupts generated based on IMOD bit
;		~~1~~~~~~~~~~~~~b			IMOD:	Interrupt at half buffer full and buffer full
;		~~~1~~~~~~~~~~~~b			CTMOD:	ABU Mode
;		~~~~0~~~~~~~~~~~b			reserved
;		~~~~~000~~~~~~~~b			SIND: 	Source Address not modified
;		~~~~~~~~01~~~~~~b			DMS:	Source Address in data space
;		~~~~~~~~~~0~~~~~b			reserved
;		~~~~~~~~~~~xxx~~b			DIND:	Destination Address post (dec/inc)remented
;		~~~~~~~~~~~~~~01b			DMD:	Destination Address in data space		
EndDMARxInitTable:						
DMATxInitTable
	.word	TxDMAptr ;;;;;;;;;;;;;;;;;;;;;;;; DMA Tx channel settings.  Use autoincrement of subaddress after 1st word	
	.word	Tx1stStart       		; DMSRC: Source is Transmit raw data buffer 
	.word	DXR1reg                    	; DMDST: Destination is McBSP DXR1 register
	.word	2*TxPKTBITS   			; DMCTR: Element count (words to transfer) is 2*total bits per character
	.word	0000000000000000b|(XEVT<<12)	; DMSFC5:
;		xxxx~~~~~~~~~~~~b			DSYN: DMA sync event is one of the McBSP Transmit Events	
;		~~~~0~~~~~~~~~~~b			DBLW: Single-word mode (each element is 16 bits)
;		~~~~~000~~~~~~~~b			reserved
;		~~~~~~~~00000000b			Frame Count: not relevant in ABU mode	 
	
	.word	0111000001000001b|(DMAptrMod<<8); DMMCR:
;		0~~~~~~~~~~~~~~~b			AUTOINIT: Auto-initialization is disabled
;		~1~~~~~~~~~~~~~~b			DINM:	Interrupts generated based on IMOD bit
;		~~1~~~~~~~~~~~~~b			IMOD:	Interrupt at half buffer full and buffer full
;		~~~1~~~~~~~~~~~~b			CTMOD:	ABU Mode
;		~~~~0~~~~~~~~~~~b			reserved
;		~~~~~xxx~~~~~~~~b			SIND: 	Source Address post (dec/inc)remented
;		~~~~~~~~01~~~~~~b			DMS:	Source Address in data space
;		~~~~~~~~~~0~~~~~b			reserved
;		~~~~~~~~~~~000~~b			DIND:	Destination Address not modified
;		~~~~~~~~~~~~~~01b			DMD:	Destination Address in data space		
EndDMATxInitTable: