/*
 *  Copyright 2002 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  
 */
/* "@(#) DSP/BIOS 4.80.208 12-06-02 (barracuda-l19)" */
/*
 *  ======== dss.c ========
 *  DSS provides a pipe(PIP) interface to the serial port audio data.
 *  DSS export two pipes: DSS_rxPipe and DSS_txPipe.  DSS_rxPipe can be
 *  read by the client to receive data from the serial port and
 *  DSS_txPipe can be written to by the client to send data to the
 *  serial port.
 *
 *  The input pipe (DSS_rxPipe) operates as follows:
 *
 *    Startup:
 *      BIOS startup            
 *      ------------            
 *      notifyWriter()
 *          |__DSS_rxPrime(0)
 *                              
 *
 *    Steady state:
 *      ISR(writer)              client(reader)
 *      -----------              --------------
 *      PIP_put()
 *          |__notifyReader()--> audio()
 *                                 |
 *      DSS_rxPrime(1)             |
 *          |__PIP_alloc()         |
 *             start DMA           |
 *                                 |__PIP_get()
 *                                    `process data`
 *                                    PIP_free()
 *                                        |__notifyWriter()
 *                                              |__DSS_rxPrime(0)
 *
 *  The output pipe (DSS_txPipe) operates as follows:
 *
 *    Startup:
 *      BIOS startup            
 *      ------------            
 *      notifyWriter()
 *          |__DSS_txPrime(0)
 *                              
 *
 *    Steady state:
 *      ISR(reader)              client(writer)
 *      -----------              --------------
 *      PIP_free()
 *          |__notifyWriter()--> audio()
 *                                 |
 *      DSS_txPrime(1)             |
 *          |__PIP_get()           |
 *             start DMA           |
 *                                 |__PIP_alloc()
 *                                    `write data`
 *                                    PIP_put()
 *                                        |__notifyReader()
 *                                              |__DSS_txPrime(0)
 */

#include <std.h>
#include <pip.h>
#include <log.h>
#include <trc.h>
#include <clk.h>

#include "dss.h"
#include "dss_priv.h"

#ifdef _EVM5510_
#include "dss_evm5510.h"
#endif

#ifdef _EDMA_
#include <csl_cache.h>
#endif

Int     DSS_error = 0;

Int     DSS_rxCnt = 0;
Int     DSS_txCnt = 0;

Int     *DSS_rxPtr = NULL;
Int     *DSS_txPtr = NULL;

DSS_Obj DSS_config = {
        0                       /*  enable tracing */
};

/*
 *  ======= DSS_txPrime ========
 *  Called when DSS_txPipe has a full buffer to be transmitted
 *  (i.e., when notifyReader() is called) and when the DSS ISR
 *  is ready for more data.
 */
#ifdef _EVM5510_
void DSS_txPrime(Arg Arg_calledByISR)
#else
void DSS_txPrime(Bool calledByISR)
#endif
{
#ifdef _EVM5510_
    Int calledByISR = ArgToInt(Arg_calledByISR);
#endif
    PIP_Obj     *txPipe = &DSS_txPipe;
    static int delay = 1;       /* or 2, 3, etc. */
    static Int nested = 0;
    
    LOG_message("DSS_txPrime(): %u", CLK_gethtime());

#if !(defined(_EDMA_) || defined(_DMA_) || defined(_EVM5510_))
    if (calledByISR) {
        DSS_computePhase(PIP_getWriterSize(txPipe));
    }
#endif

    if (nested) {       /* prohibit recursive call via PIP_get() */
        return;
    }

    if (delay) {      /* ensure that output does not start too soon */
        delay--;
        return;
    }

    nested = 1;

    if (DSS_txCnt == 0 && PIP_getReaderNumFrames(txPipe) > 0) {
        Int count;
#ifndef _EVM5510_
        Int i;
        MdInt *dst;
#endif
        PIP_get(txPipe);

        /* must set 'Ptr' before 'Cnt' to synchronize with isr() */
        DSS_txPtr = PIP_getReaderAddr(txPipe);

        /* ensure bit 0 of DAC word is 0; AIC uses bit 0 to request control */
        count = (sizeof(Int) / sizeof(MdInt)) * PIP_getReaderSize(txPipe);
#ifndef _EVM5510_
        for (i = count, dst = (MdInt *)DSS_txPtr; i > 0; i--) {
            *dst++ = 0xfffe & *dst;
        }
#endif
        DSS_txCnt = count;

#if defined(_EDMA_) || defined(_DMA_) || defined(_EVM5510_)
        DSS_dmaTxStart(DSS_txPtr, DSS_txCnt);
#endif
    }
    else if (calledByISR && (DSS_error & DSS_TXERR) == 0) {
        if (DSS_config.enable) {
            TRC_disable(TRC_GBLTARG);
        }
        LOG_error("transmit buffer underflow: %u", CLK_gethtime());
        DSS_error |= DSS_TXERR;
    }

    nested = 0;
}

/*
 *  ======= DSS_rxPrime ========
 *  Called when DSS_rxPipe has an empty buffer to be filled;
 *  e.g., when notifyWriter() is called) and when the DSS ISR
 *  is ready to fill another buffer.
 */
#ifdef _EVM5510_
void DSS_rxPrime(Arg Arg_calledByISR)
#else
void DSS_rxPrime(Bool calledByISR)
#endif
{
#ifdef _EVM5510_
    Int calledByISR = ArgToInt(Arg_calledByISR);
#endif

    PIP_Obj     *rxPipe = &DSS_rxPipe;
    static Int  nested = 0;
    
    LOG_message("DSS_rxPrime(): %u", CLK_gethtime());

#if !(defined(_EDMA_) || defined(_DMA_)|| defined(_EVM5510_))
    if (calledByISR) {
        DSS_computePhase(PIP_getWriterSize(rxPipe));
    }
#endif

    if (nested) {       /* prohibit recursive call via PIP_alloc() */
        return;
    }
    nested = 1;

    if (DSS_rxCnt == 0 && PIP_getWriterNumFrames(rxPipe) > 0) {
        PIP_alloc(rxPipe);

        /* must set 'Ptr' before 'Cnt' to synchronize with isr() */
        DSS_rxPtr = PIP_getWriterAddr(rxPipe);
        DSS_rxCnt = (sizeof(Int) / sizeof(MdInt)) * PIP_getWriterSize(rxPipe);

#if defined(_EDMA_) || defined(_DMA_) || defined(_EVM5510_)
        DSS_dmaRxStart(DSS_rxPtr, DSS_rxCnt);
#endif
    }
    else if (calledByISR && (DSS_error & DSS_RXERR) == 0) {
        if (DSS_config.enable) {
            TRC_disable(TRC_GBLTARG);
        }
        LOG_error("receive buffer overflow: %u", CLK_gethtime());
        DSS_error |= DSS_RXERR;
    }

    nested = 0;
}

#ifdef _EDMA_
/*
 *  ======== DSS_dmaInit ========
 *  Initialise EDMA Controller
 */
Void DSS_dmaInit(Void)
{
    LOG_message("DSS_dmaInit(): %u", CLK_gethtime());

    /* General EDMA Initialization */
    EDMA_RSET(EER, 0x0000);     /* Disable all events */
    EDMA_RSET(ECR, 0xffff);     /* Clear all pending events */
    EDMA_RSET(CIER, 0x0000);    /* Disable all events to Interrupt */
    EDMA_RSET(CIPR, 0xffff);    /* Clear all pending Queued EDMA ints */

    /* Enable Rx/Tx DMA Complete Interrupts to the CPU */
    EDMA_RSET(CIER, DSS_RXDONE | DSS_TXDONE);
}

/*
 *  ======= DSS_dmaRxStart ========
 */
Void DSS_dmaRxStart(Void *dst, Int nsamps)
{
    LOG_message("DSS_dmaRxstart(): %u", CLK_gethtime());
    
    CACHE_clean(CACHE_L2, dst, nsamps);

    /* Reconfig EDMA channel for next receive buffer */
    EDMA_RSETH(DSS_hEdmaRint0, CNT, (Uns) nsamps);
    EDMA_RSETH(DSS_hEdmaRint0, DST, (Uns) dst);

    EDMA_RSET(EER, 0x3000);     /* Enable McBSP0 Rx/Tx Events to the DMA */
}

/*
 *  ======= DSS_dmaTxStart ========
 */
Void DSS_dmaTxStart(Void *src, Int nsamps)
{
    static Int startup = 1;

    LOG_message("DSS_dmaTxstart(): %u", CLK_gethtime());
    
    CACHE_flush(CACHE_L2, src, nsamps);

    if (startup) {
        startup = 0;
        DSS_spWrite(0); DSS_spWrite(0);
        /* EDMA_RSET(ECR, 0x3000);    /Clear any previous McBSP Events */
    }

    /* Reconfig EDMA channel for next transmit buffer */
    EDMA_RSETH(DSS_hEdmaXint0, SRC, (Uns) src);
    EDMA_RSETH(DSS_hEdmaXint0, CNT, (Uns) nsamps);

    EDMA_RSET(EER, 0x3000);     /* Enable McBSP0 Rx/Tx Events to the DMA */
}
#endif

#ifdef _DMA_
/*
 *  ======= DSS_dmaRxStart ========
 */
void DSS_dmaRxStart(void *dst, Int nsamps)
{
    DMA_RSETH(DSS_hDmaRint0, SRC,(Int)(&DSS_hMcbsp0->baseAddr[_MCBSP_DRR_OFFSET]));
    DMA_RSETH(DSS_hDmaRint0, DST, (Uns)dst);
    DMA_RSETH(DSS_hDmaRint0, XFRCNT, (0x1 << 16) + nsamps / (sizeof(Int) / sizeof(MdInt)));
    DMA_start(DSS_hDmaRint0);
}

/*
 *  ======= DSS_dmaTxStart ========
 */
void DSS_dmaTxStart(void *src, Int nsamps)
{
    static Int startup = 1;

    if (startup) {
        startup = 0;
        DSS_spWrite(0); DSS_spWrite(0);
    }
    DMA_RSETH(DSS_hDmaXint0, SRC, (Uns)src);
    DMA_RSETH(DSS_hDmaXint0, DST,(Int)(&DSS_hMcbsp0->baseAddr[_MCBSP_DXR_OFFSET]));
    DMA_RSETH(DSS_hDmaXint0, XFRCNT, (0x1 << 16) + nsamps / (sizeof(Int) / sizeof(MdInt)));
    DMA_start(DSS_hDmaXint0);
}
#endif

#ifdef _EVM5510_
/*
 *  ======= DSS_dmaRxStart ========
 */
void DSS_dmaRxStart(void *dst, Int nsamps)
{
    aic27_capture(dst, nsamps);
}

/*
 *  ======= DSS_dmaTxStart ========
 */
void DSS_dmaTxStart(void *src, Int nsamps)
{
    aic27_play(src, nsamps);
}
#endif