#define DMAMP_RX_3_MAXCNT1      (DMA_BASE+0x00F0)#define DMAMP_RX_3_BASE1        (DMA_BASE+0x00F4)#define DMAMP_RX_3_CURRENT1     (DMA_BASE+0x00F8)#define DMAMM_0_CONTROL         (DMA_BASE+0x0100)#define DMAMM_0_INTERRUPT       (DMA_BASE+0x0104)#define DMAMM_0_STATUS          (DMA_BASE+0x010C)#define DMAMM_0_BCR0            (DMA_BASE+0x0110)#define DMAMM_0_BCR1            (DMA_BASE+0x0114)#define DMAMM_0_SAR_BASE0       (DMA_BASE+0x0118)#define DMAMM_0_SAR_BASE1       (DMA_BASE+0x011C)#define DMAMM_0_SAR_CURRENT0    (DMA_BASE+0x0124)#define DMAMM_0_SAR_CURRENT1    (DMA_BASE+0x0128)#define DMAMM_0_DAR_BASE0       (DMA_BASE+0x012C)#define DMAMM_0_DAR_BASE1       (DMA_BASE+0x0130)#define DMAMM_0_DAR_CURRENT0    (DMA_BASE+0x0134)#define DMAMM_0_DAR_CURRENT1    (DMA_BASE+0x013C)#define DMAMM_1_CONTROL         (DMA_BASE+0x0140)#define DMAMM_1_INTERRUPT       (DMA_BASE+0x0144)#define DMAMM_1_STATUS          (DMA_BASE+0x014C)#define DMAMM_1_BCR0            (DMA_BASE+0x0150)#define DMAMM_1_BCR1            (DMA_BASE+0x0154)#define DMAMM_1_SAR_BASE0       (DMA_BASE+0x0158)#define DMAMM_1_SAR_BASE1       (DMA_BASE+0x015C)#define DMAMM_1_SAR_CURRENT0    (DMA_BASE+0x0164)#define DMAMM_1_SAR_CURRENT1    (DMA_BASE+0x0168)#define DMAMM_1_DAR_BASE0       (DMA_BASE+0x016C)#define DMAMM_1_DAR_BASE1       (DMA_BASE+0x0170)#define DMAMM_1_DAR_CURRENT0    (DMA_BASE+0x0174)#define DMAMM_1_DAR_CURRENT1    (DMA_BASE+0x017C)#define DMAMP_RX_5_CONTROL      (DMA_BASE+0x0200)#define DMAMP_RX_5_INTERRUPT    (DMA_BASE+0x0204)#define DMAMP_RX_5_PPALLOC      (DMA_BASE+0x0208)#define DMAMP_RX_5_STATUS       (DMA_BASE+0x020C)#define DMAMP_RX_5_REMAIN       (DMA_BASE+0x0214)#define DMAMP_RX_5_MAXCNT0      (DMA_BASE+0x0220)#define DMAMP_RX_5_BASE0        (DMA_BASE+0x0224)#define DMAMP_RX_5_CURRENT0     (DMA_BASE+0x0228)#define DMAMP_RX_5_MAXCNT1      (DMA_BASE+0x0230)#define DMAMP_RX_5_BASE1        (DMA_BASE+0x0234)#define DMAMP_RX_5_CURRENT1     (DMA_BASE+0x0238)#define DMAMP_TX_4_CONTROL      (DMA_BASE+0x0240)#define DMAMP_TX_4_INTERRUPT    (DMA_BASE+0x0244)#define DMAMP_TX_4_PPALLOC      (DMA_BASE+0x0248)#define DMAMP_TX_4_STATUS       (DMA_BASE+0x024C)#define DMAMP_TX_4_REMAIN       (DMA_BASE+0x0254)#define DMAMP_TX_4_MAXCNT0      (DMA_BASE+0x0260)#define DMAMP_TX_4_BASE0        (DMA_BASE+0x0264)#define DMAMP_TX_4_CURRENT0     (DMA_BASE+0x0268)#define DMAMP_TX_4_MAXCNT1      (DMA_BASE+0x0270)#define DMAMP_TX_4_BASE1        (DMA_BASE+0x0274)#define DMAMP_TX_4_CURRENT1     (DMA_BASE+0x0278)#define DMAMP_RX_7_CONTROL      (DMA_BASE+0x0280)#define DMAMP_RX_7_INTERRUPT    (DMA_BASE+0x0284)#define DMAMP_RX_7_PPALLOC      (DMA_BASE+0x0288)#define DMAMP_RX_7_STATUS       (DMA_BASE+0x028C)#define DMAMP_RX_7_REMAIN       (DMA_BASE+0x0294)#define DMAMP_RX_7_MAXCNT0      (DMA_BASE+0x02A0)#define DMAMP_RX_7_BASE0        (DMA_BASE+0x02A4)#define DMAMP_RX_7_CURRENT0     (DMA_BASE+0x02A8)#define DMAMP_RX_7_MAXCNT1      (DMA_BASE+0x02B0)#define DMAMP_RX_7_BASE1        (DMA_BASE+0x02B4)#define DMAMP_RX_7_CURRENT1     (DMA_BASE+0x02B8)#define DMAMP_TX_6_CONTROL      (DMA_BASE+0x02C0)#define DMAMP_TX_6_INTERRUPT    (DMA_BASE+0x02C4)#define DMAMP_TX_6_PPALLOC      (DMA_BASE+0x02C8)#define DMAMP_TX_6_STATUS       (DMA_BASE+0x02CC)#define DMAMP_TX_6_REMAIN       (DMA_BASE+0x02D4)#define DMAMP_TX_6_MAXCNT0      (DMA_BASE+0x02E0)#define DMAMP_TX_6_BASE0        (DMA_BASE+0x02E4)#define DMAMP_TX_6_CURRENT0     (DMA_BASE+0x02E8)#define DMAMP_TX_6_MAXCNT1      (DMA_BASE+0x02F0)#define DMAMP_TX_6_BASE1        (DMA_BASE+0x02F4)#define DMAMP_TX_6_CURRENT1     (DMA_BASE+0x02F8)#define DMAMP_RX_9_CONTROL      (DMA_BASE+0x0300)#define DMAMP_RX_9_INTERRUPT    (DMA_BASE+0x0304)#define DMAMP_RX_9_PPALLOC      (DMA_BASE+0x0308)#define DMAMP_RX_9_STATUS       (DMA_BASE+0x030C)#define DMAMP_RX_9_REMAIN       (DMA_BASE+0x0314)#define DMAMP_RX_9_MAXCNT0      (DMA_BASE+0x0320)#define DMAMP_RX_9_BASE0        (DMA_BASE+0x0324)#define DMAMP_RX_9_CURRENT0     (DMA_BASE+0x0328)#define DMAMP_RX_9_MAXCNT1      (DMA_BASE+0x0330)#define DMAMP_RX_9_BASE1        (DMA_BASE+0x0334)#define DMAMP_RX_9_CURRENT1     (DMA_BASE+0x0338)#define DMAMP_TX_8_CONTROL      (DMA_BASE+0x0340)#define DMAMP_TX_8_INTERRUPT    (DMA_BASE+0x0344)#define DMAMP_TX_8_PPALLOC      (DMA_BASE+0x0348)#define DMAMP_TX_8_STATUS       (DMA_BASE+0x034C)#define DMAMP_TX_8_REMAIN       (DMA_BASE+0x0354)#define DMAMP_TX_8_MAXCNT0      (DMA_BASE+0x0360)#define DMAMP_TX_8_BASE0        (DMA_BASE+0x0364)#define DMAMP_TX_8_CURRENT0     (DMA_BASE+0x0368)#define DMAMP_TX_8_MAXCNT1      (DMA_BASE+0x0370)#define DMAMP_TX_8_BASE1        (DMA_BASE+0x0374)#define DMAMP_TX_8_CURRENT1     (DMA_BASE+0x0378)#define DMA_ARBITRATION         (DMA_BASE+0x0380)#define DMA_INTERRUPT           (DMA_BASE+0x03C0)/* 8001_0000 - 8001_ffff: Ether MAC */#define MAC_OFFSET              0x010000#define MAC_BASE                (EP93XX_AHB_BASE|MAC_OFFSET)#define MAC_RXCTL               (MAC_BASE+0x00)	/* 2-RW Rx  Control */#define MAC_TXCTL               (MAC_BASE+0x04)	/* 1-RW Tx Control */#define MAC_TESTCTL             (MAC_BASE+0x08)	/* 1-RW Test Control */#define MAC_MIICMD              (MAC_BASE+0x10)	/* 2-RW MII(Media Independent Intf) Command */#define MAC_MIIDATA             (MAC_BASE+0x14)	/* 2-RW MII Data */#define MAC_MIISTS              (MAC_BASE+0x18)	/* 1-RO MII Status */#define MAC_SELFCTL             (MAC_BASE+0x20)	/* 1-RW Self Control for LED interface */#define MAC_INTEN               (MAC_BASE+0x24)	/* 4-RW Intrrpt Enable */#define MAC_INTSTSP             (MAC_BASE+0x28)	/* 4-RW Intrrpt Status Preserve */#define MAC_INTSTSC             (MAC_BASE+0x2C)	/* 4-RO Intrrpt Status Clear */#define MAC_DIAGAD              (MAC_BASE+0x38)	/* 4-RW Diag Addr (debug only) */#define MAC_DIAGDATA            (MAC_BASE+0x3C)	/* 4-RW Diag Data (debug only) */#define MAC_GT                  (MAC_BASE+0x40)	/* 4-RW General Timer */#define MAC_FCT                 (MAC_BASE+0x44)	/* 4-RO Flow Control Timer */#define MAC_FCF                 (MAC_BASE+0x48)	/* 4-RW Flow Control Format */#define MAC_AFP                 (MAC_BASE+0x4C)	/* 1-RW Addr Filter Pointer */#define MAC_HASHTB              (MAC_BASE+0x50)	/* 8-RW Logical Addr Filter (Hash Table) */#define MAC_INDAD               (MAC_BASE+0x50)	/* 6-RW Individual Addr, IA */#define MAC_INDAD_UPPER         (MAC_BASE+0x54)	/* 6-RW Individual Addr, IA */#define MAC_FER                 (MAC_BASE+0x60)	/* 4-RW Cardbus Functn Event Reg */#define MAC_FERMASK             (MAC_BASE+0x64)	/* 4-RW Cardbus Functn Event Mask Reg */#define MAC_FPSR                (MAC_BASE+0x68)	/* 4-RO Cardbus Functn Present Status Reg */#define MAC_FFER                (MAC_BASE+0x6C)	/* 4-RW Cardbus Functn Force Event Reg */#define MAC_TXCOLLCNT           (MAC_BASE+0x70)	/* 2-RW Tx Collision Count */#define MAC_RXMISSCNT           (MAC_BASE+0x74)	/* 2-RW Rx Miss Count */#define MAC_RXRUNTCNT           (MAC_BASE+0x78)	/* 2-RW Rx Runt Count */#define MAC_BMCTL               (MAC_BASE+0x80)	/* 1-RW Bus Master Control */#define MAC_BMSTS               (MAC_BASE+0x84)	/* 1-RO Bus Master Status */#define MAC_RXBCA               (MAC_BASE+0x88)	/* 4-RO Rx buffer current address */#define MAC_TXBCA               (MAC_BASE+0x8C)	/* 4-RO Tx buffer current address */#define MAC_RXDBA               (MAC_BASE+0x90)	/* 4-RW Rx Descrptr Queue Base Addr */#define MAC_RXDBL               (UINT16*)(MAC_BASE+0x94)	/* 2-RW Rx Descrptr Queue Base Length */#define MAC_RXDCA               (MAC_BASE+0x98)	/* 4-RW Rx Descrptr Current Addr */#define MAC_RXDEQ               (MAC_BASE+0x9C)	/* 2-RW Rx Descrptr Enqueue */#define MAC_RXSBA               (MAC_BASE+0xA0)	/* 4-RW Rx Status Queue Base Addr */#define MAC_RXSBL               (UINT16*)(MAC_BASE+0xA4)	/* 2-RW Rx Status Queue Base Length */#define MAC_RXSCA               (MAC_BASE+0xA8)	/* 4-RW Rx Status Current Addr */#define MAC_RXSEQ               (MAC_BASE+0xAC)	/* 2-RW Rx Status Enqueue */#define MAC_TXDBA               (MAC_BASE+0xB0)	/* 4-RW Tx Descrptr Queue Base Addr */#define MAC_TXDBL               (MAC_BASE+0xB4)	/* 2-RW Tx Descrptr Queue Base Length */#define MAC_TXDCL               (MAC_BASE+0xB6)	/* 2-RW Tx Descrptr Queue Current Length */#define MAC_TXDCA               (MAC_BASE+0xB8)	/* 4-RW Tx Descrptr Current Addr */#define MAC_TXDEQ               (MAC_BASE+0xBC)	/* 2-RW Tx Descrptr Enqueue */#define MAC_TXSBA               (MAC_BASE+0xC0)	/* 4-RW Tx status Queue Base Addr */#define MAC_TXSBL               (MAC_BASE+0xC4)	/* 2-RW Tx Status Queue Base Length */#define MAC_TXSCL               (MAC_BASE+0xC6)	/* 2-RW Tx Status Queue Current Length */#define MAC_TXSCA               (MAC_BASE+0xC8)	/* 4-RW Tx Status Current Addr */#define MAC_TXSEQ               (MAC_BASE+0xCC)	/* 4-RW Tx Status Current Addr */#define MAC_RXBTH               (MAC_BASE+0xD0)	/* 4-RW Rx Buffer Thrshold */#define MAC_TXBTH               (MAC_BASE+0xD4)	/* 4-RW Tx Buffer Thrshold */#define MAC_RXSTH               (MAC_BASE+0xD8)	/* 4-RW Rx Status Thrshold */#define MAC_TXSTH               (MAC_BASE+0xDC)	/* 4-RW Tx Status Thrshold */#define MAC_RXDTH               (MAC_BASE+0xE0)	/* 4-RW Rx Descrptr Thrshold */#define MAC_TXDTH               (MAC_BASE+0xE4)	/* 4-RW Tx Descrptr Thrshold */#define MAC_MAXFL               (MAC_BASE+0xE8)	/* 4-RW Maximum Frame Length */#define MAC_RXHLEN              (MAC_BASE+0xEC)	/* 2-RW Rx Header Length */#define MAC_CFG_REG0            (MAC_BASE+0x100)	/* config registers 0-2 */#define MAC_CFG_REG1            (MAC_BASE+0x104)	/*   */#define MAC_CFG_REG2            (MAC_BASE+0x108)	/*   *//* 8002_0000 - 8002_ffff: USH */#define USB_OFFSET              0x020000#define USB_BASE                (EP93XX_AHB_BASE|USB_OFFSET)#define HCREVISION              (USB_BASE+0x00)#define HCCONTROL               (USB_BASE+0x04)#define HCCOMMANDSTATUS         (USB_BASE+0x08)#define HCINTERRUPTSTATUS       (USB_BASE+0x0C)#define HCINTERRUPTENABLE       (USB_BASE+0x10)#define HCINTERRUPTDISABLE      (USB_BASE+0x14)#define HCHCCA                  (USB_BASE+0x18)#define HCPERIODCURRENTED       (USB_BASE+0x1C)#define HCCONTROLHEADED         (USB_BASE+0x20)#define HCCONTROLCURRENTED      (USB_BASE+0x24)#define HCBULKHEADED            (USB_BASE+0x28)#define HCBULKCURRENTED         (USB_BASE+0x2C)#define HCDONEHEAD              (USB_BASE+0x30)#define HCFMINTERVAL            (USB_BASE+0x34)#define HCFMREMAINING           (USB_BASE+0x38)#define HCFMNUMBER              (USB_BASE+0x3C)#define HCPERIODICSTART         (USB_BASE+0x40)#define HCLSTHRESHOLD           (USB_BASE+0x44)#define HCRHDESCRIPTORA         (USB_BASE+0x48)#define HCRHDESCRIPTORB         (USB_BASE+0x4C)#define HCRHSTATUS              (USB_BASE+0x50)#define HCRHPORTSTATUS0         (USB_BASE+0x54)#define HCRHPORTSTATUS1         (USB_BASE+0x58)#define HCRHPORTSTATUS2         (USB_BASE+0x5C)/* some tests used these registers names which are typos of original ones */#define HCRHPROTSTATUS0         (USB_BASE+0x54)#define HCRHPROTSTATUS1         (USB_BASE+0x58)#define HCRHPROTSTATUS2         (USB_BASE+0x5C)/* additional registers for controlling the AHB-HCI interface */#define USBCTRL                 (USB_BASE+0x80)#define USBHCI                  (USB_BASE+0x84)#define USBTXTEST               (USB_BASE+0x88)#define USBRXTEST               (USB_BASE+0x8C)/* 8003_0000 - 8003_ffff: Raster */#define RASTER_OFFSET           0x030000#define RASTER_BASE             (EP93XX_AHB_BASE|RASTER_OFFSET)