data = io.irq[IRQD];			//DBG_PRINT("@0x%08x: IRQSTATD(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;		case IOMD_IRQREQD:			data = io.irq[IRQD] & io.irqmask[IRQD];			//DBG_PRINT("@0x%08x: IRQREQD(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;				case IOMD_DMAMASK:			data = io.irqmask[IRQDMA];			//DBG_PRINT("@0x%08x: DMAMASK(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;		case IOMD_DMASTAT:			data = io.irq[IRQDMA];			//DBG_PRINT("@0x%08x: DMASTAT(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;		case IOMD_DMAREQ:			data = io.irq[IRQDMA] & io.irqmask[IRQDMA];			//DBG_PRINT("@0x%08x: DMAREQ(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;				case IOMD_FIQSTAT:			data = io.fiq[FIQ];			//DBG_PRINT("@0x%08x: FIQSTAT(0x%08x) -> %02x\n",			//	PC - 8, addr, data );			break;		case IOMD_FIQREQ:			data = io.fiqmask[FIQ] & io.fiqmask[FIQ];			//DBG_PRINT("@0x%08x: FIQREQ(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;		case IOMD_KCTRL:			data = io.kb_stat;			//DBG_PRINT("@0x%08x: KCTRL(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;				case IOMD_KARTRX:			io.kb_stat &= ~KB_RXF;			CLR_IRQ(IRQ_KEYBOARDRX);			data = io.kb_data;			ps7500_kb_next(state);			//DBG_PRINT("@0x%08x: KARTRX(0x%08x) -> %02x\n",			//	PC - 8, addr, data);			break;		}		return data;							}			if ((addr >= NET_ADDR_START) && (addr < NET_ADDR_END)) {		offset = (addr - NET_ADDR_START) >> 2;		DBG_PRINT("@0x%08x: Ethernet reg %03x read byte start\n",			PC - 8, offset);		//data = nic_read(0, state, offset);		DBG_PRINT("@0x%08x: Ethernet reg %03x read byte 0x%02x\n",			PC - 8, offset, data);		return data;	}		DBG_PRINT("@0x%08x: io_read_byte(0x%08x) -> 0x%02x\n", PC - 8,			 addr, data);	return data;}ARMword ps7500_io_read_halfword(ARMul_State *state, ARMword addr){	DBG_PRINT("SKYEYE: ps7500_io_read_halfword error\n");}FILE *fo = NULL;#define RAMSTART	0x10000000#define BANKOFFSET	0x04000000#define BANKSIZE	0x00400000ARMword ps7500_io_read_word(ARMul_State *state, ARMword addr){	ARMword data = 0;	ARMword data2;	ARMword b;	ARMword i;		if (fo == NULL) {		DBG_PRINT("Dumping memory\n");		fo = fopen("mem.dump", "w");		for (b=0; b < 4; b++) {			for (i=0; i < BANKSIZE; i = i + 4) {				data2 = real_read_word(state,					 RAMSTART + (b * BANKOFFSET) + i); 				fwrite(&data2, 4, 1, fo);			}		}		fclose(fo);		DBG_PRINT("Done\n");	}					DBG_PRINT("io_read_word(0x%08x) = 0x%08x\n", addr, data);	return data;}void ps7500_io_write_byte(ARMul_State *state, ARMword addr, ARMword data){	ARMword offset;		if ((addr >= IOMD_ADDR_START) && (addr < IOMD_ADDR_END)) {		offset = addr - IOMD_ADDR_START;		switch (offset) {				case IOMD_CONTROL:			io.iocr_write = data & 0x03;			DBG_PRINT("@0x%08x: IOCR(0x%08x) <- 0x%02x\n",				PC - 8, addr, data);			break;					case IOMD_IRQMASKA:			io.irqmask[IRQA] = data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: IRQMASKA(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_IRQCLRA:			io.irq[IRQA] &= ~data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: IRQCLRA(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_IRQMASKB:			io.irqmask[IRQB]= data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: IRQMSKB(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_IRQMASKC:			io.irqmask[IRQC] = data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: IRQMASKC(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_IRQMASKD:			io.irqmask[IRQD] = data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: IRQMASKD(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;				case IOMD_DMAMASK:			io.irqmask[IRQDMA] = data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: DMAMSK(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;				case IOMD_FIQMASK:			io.fiqmask[FIQ] = data;			ps7500_update_int(state);			//DBG_PRINT("@0x%08x: FIQMSK(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;					case IOMD_CLKCTL:			//DBG_PRINT("@0x%08x: CLKCTL(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;					case IOMD_T0CNTL:			io.tcd_reload[0] = (io.tcd_reload[0] & 0xff00) | data;			//DBG_PRINT("@0x%08x: T0CNTL(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_T0CNTH:			io.tcd_reload[0] = (io.tcd_reload[0] & 0x00ff) | data;			//DBG_PRINT("T0CNTH(0x%08x) <- 0x%02x\n", PC - 8, addr, data);			break;					case IOMD_T0GO:			io.tcd[0] = io.tcd_reload[0];			//DBG_PRINT("@0x%08x: T0GO(0x%08x) <- 0x%02x\n",				//	PC - 8, addr, data);			break;					case IOMD_T1CNTL:			io.tcd_reload[1] = (io.tcd_reload[1] & 0xff00) | data;			DBG_PRINT("@0x%08x: T1CNTL(0x%08x) <- 0x%02x\n",				PC - 8, addr, data);			break;		case IOMD_T1CNTH:			io.tcd_reload[1] = (io.tcd_reload[1] & 0x00ff) | data;			//DBG_PRINT("T1CNTH(0x%08x) <- 0x%02x\n", PC - 8, addr, data);			break;					case IOMD_T1GO:			io.tcd[1] = io.tcd_reload[1];			//DBG_PRINT("@0x%08x: T1GO(0x%08x) <- 0x%02x\n",				//	PC - 8, addr, data);			break;					case IOMD_ROMCR0:			//DBG_PRINT("@0x%08x: ROMCR0(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_ROMCR1:			//DBG_PRINT("@0x%08x: ROMCR1(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;		case IOMD_DRAMCR:			//DBG_PRINT("@0x%08x: DRAMCR(0x%08x) <- 0x%02x\n",			//	PC - 8, addr, data);			break;					case IOMD_VIDCR:			DBG_PRINT("@0x%08x: VIDCR(0x%08x) <- 0x%02x\n",				PC - 8, addr, data);			if ((data & 0x20) && (io.lcd_started == 0)) {				DBG_PRINT("Start LCD\n");				//lcd_enable(state, 640, 480, 8);				io.lcd_started = 1;			}			io.vidcr = data;			break;					case IOMD_KCTRL:			if (data & 0x08) 		// Enable				io.kb_stat = KB_SKC | KB_SKD | KB_ENA | KB_TXE;			else				// Disable				io.kb_stat = 0;			//DBG_PRINT("@0x%08x: KCTRL(0x%08x) <- 0x%02x\n", 			//	PC - 8, addr, data);			break;					case IOMD_KARTTX:			//DBG_PRINT("@0x%08x: KARTTX(0x%08x) <- 0x%02x\n", 			//	PC - 8, addr, data);			// Send a character to PS2 keyboard.			// This is a keyboard command.			// Clear TXEmpty, clear TX interrupt, set TXBusy			// Queue an ACK (0xfa) response			// If command is RESET (0xff), then			// also queue a reset done (0xaa) response			io.kb_stat &= ~ KB_TXE;			CLR_IRQ(IRQ_KEYBOARDTX);			io.kb_stat |= KB_TXB ;			io.kb_delay = 10;			ps7500_kb_queue(state, 0xfa);			if (data == 0xff)  				ps7500_kb_queue(state, 0xaa);			break;				default:			DBG_PRINT("@0x%08x: io_write_byte(0x%08x) <- 0x%02x\n", 				PC - 8, addr, data);			break;		}		return;	} 		if (addr == VIDEO_ADDR) {		DBG_PRINT("@0x%08x: Video register write 0x%08x\n", PC - 8, data);		return;	}		if ((addr >= NET_ADDR_START) && (addr <= NET_ADDR_END)) {		offset = (addr - NET_ADDR_START) >> 2;		DBG_PRINT("@0x%08x: Ethernet reg %03x write byte 0x%02x\n",			PC - 8, offset, data);		//nic_write(0, state, offset, data);		return;	}		DBG_PRINT("@0x%08x: io_write_byte(0x%08x) <- 0x%08x\n",		PC - 8, addr, data);}void ps7500_io_write_halfword(ARMul_State *state, ARMword addr, ARMword data){	DBG_PRINT("io_write_halfword(0x%08x) <- 0x%08x\n", addr, data);}void ps7500_io_write_word(ARMul_State *state, ARMword addr, ARMword data){       	ARMword offset;		if ((addr >= IOMD_ADDR_START) && ( addr < IOMD_ADDR_END)) {		offset = addr - IOMD_ADDR_START;		switch (offset) {		case IOMD_CURSINIT:			DBG_PRINT("CURSINIT <- 0x%08x\n", data);			break;		case IOMD_VIDEND:			io.vidend = data;			DBG_PRINT("VIDEND <- 0x%08x\n", data);			break;		case IOMD_VIDSTART:			io.vidstart = data;			io.lcd_addr_begin = data;			DBG_PRINT("VIDSTART <- 0x%08x\n", data);			break;		case IOMD_VIDINIT:			io.vidinit = data;			DBG_PRINT("VIDINIT <- 0x%08x\n", data);			break;					default:			DBG_PRINT("io_write_word(0x%08x) <- 0x%08x\n", 				addr - 0x03200000, data);			break;		}		return;	} 		if (addr == VIDEO_ADDR) {		DBG_PRINT("Video register write <- 0x%08x\n", data);		return;	}		// Network data sometimes written in 16 bit pieces	if ((addr >= NET_ADDR_START) && (addr < NET_ADDR_END)) {		offset = (addr - NET_ADDR_START) >> 2;		if (offset != 0x10) {			printf("Net word write at bad address\n");			exit(1);		}		DBG_PRINT("Net data write <- 0x%04x\n", data & 0xffff);		//nic_write(0, state, offset, data & 0xff);		//nic_write(0, state, offset, (data >> 8) & 0xff);		return;	}			DBG_PRINT("io_write_word(0x%08x) <- 0x%08x\n", addr, data);}void ps7500_mach_init(ARMul_State *state, machine_config_t *this_mach){	ARMul_SelectProcessor(state, ARM_v4_Prop);        //chy 2004-05-09, set lateabtSig        state->lateabtSig = HIGH;	this_mach->mach_io_do_cycle = 		ps7500_io_do_cycle;	this_mach->mach_io_reset = 		ps7500_io_reset;        this_mach->mach_io_read_byte = 		ps7500_io_read_byte;        this_mach->mach_io_write_byte = 	ps7500_io_write_byte;        this_mach->mach_io_read_halfword = 	ps7500_io_read_halfword;        this_mach->mach_io_write_halfword = 	ps7500_io_write_halfword;	this_mach->mach_io_read_word = 		ps7500_io_read_word;	this_mach->mach_io_write_word = 	ps7500_io_write_word;		this_mach->mach_update_int =            ps7500_update_int;	this_mach->mach_set_intr = ps7500_set_intr;	this_mach->mach_pending_intr = ps7500_pending_intr;	this_mach->mach_update_intr = ps7500_update_intr;		/*	state->mach_io.lcd_is_enable = (ARMword *)&io.lcd_is_enable;	state->mach_io.lcd_addr_begin = (ARMword *)&io.lcd_addr_begin;	state->mach_io.lcd_addr_end = (ARMword *)&io.lcd_addr_end;	*/	state->mach_io.ts_int		=(ARMword *)&io.ts_int;	state->mach_io.ts_is_enable	=(ARMword *)&io.ts_is_enable;		state->mach_io.ts_addr_begin	=(ARMword *)&io.ts_addr_begin;		state->mach_io.instr		=(ARMword *)io.irq;	state->mach_io.net_int		=(ARMword *)io.net_int;		state->mach_io.net_flag		=(ARMword *)&io.net_flag;		printf("%02x %02x\n", state->mach_io.instr, state->mach_io.net_int);}ARMbyte scancode_alpha[] = {	0x1c, 0x32, 0x21, 0x23, 0x24, 0x2b, 0x34, 0x33,	0x43, 0x3b, 0x42, 0x4b, 0x3a, 0x31, 0x44, 0x4d,	0x15, 0x2d, 0x1b, 0x2c, 0x3c, 0x2a, 0x1d, 0x22,	0x35, 0x1a};	ARMbyte scancode_number[] = {	0x45, 0x16, 0x1e, 0x26, 0x25, 0x2e, 0x36, 0x3d,	0x3e, 0x46}; ARMbyte ps7500_getcode(ARMbyte c){	if ((c >= 'a') && (c <= 'z')) 		return scancode_alpha[c - 'a'];	if ((c >= '0') && (c <= '9'))		return scancode_number[c - '0'];	if (c == '\n')		return 0x5a;	if (c == '.')		return 0x49;	if (c == '/')		return 0x4a;	return 0x49;}