.include  	"LF2407regs.h"
            .ref  		ADINIT,ADCINT_ISR,AD,FFT32,ADCHANN
            .def        INT1RET
            .global		_c_int0
;--------------------------------------         
         	.sect 		".vectors"
RSVECT   	B  	  _c_int0    ; 00
INT1	    B	  INT1_ISR	 ; 02
INT2	    B	  PHANTOM	 ; 04
INT3	    B	  PHANTOM	 ; 06
INT4	    B	  PHANTOM	 ; 08
INT5	    B	  PHANTOM	 ; 0A
INT6	    B	  PHANTOM	 ; 0C

	     	.sect		".pvecs"
PVECTORS	
        B	PHANTOM		; Reserved pvector addr offset 
		B	PHANTOM	    ; pvector addr offset 0x01 - XINT1
		B	PHANTOM		; Reserved pvector addr offset 
		B	PHANTOM		; Reserved pvector addr offset 
		B	ADCINT_ISR	; pvector addr offset 0x04 - ADC
		B	PHANTOM		; pvector addr offset 0x05 - SPI RX/TX and/or RX Overrun
		B	PHANTOM		; pvector addr offset 0x06 - SCI RX interrupt
		B	PHANTOM		; pvector addr offset 0x07 - SCI TX interrupt
		B	PHANTOM		; Reserved pvector addr offset (0x08) 
		B	PHANTOM		; Reserved pvector addr offset (0x09)
		B	PHANTOM		; Reserved pvector addr offset (0x0a)
		B	PHANTOM		; Reserved pvector addr offset (0x0b)
		B	PHANTOM		; Reserved pvector addr offset (0x0c)
		B	PHANTOM		; Reserved pvector addr offset (0x0d)
		B	PHANTOM		; Reserved pvector addr offset (0x0e)
		B	PHANTOM		; Reserved pvector addr offset (0x0f)
		B	PHANTOM  	; pvector addr offset 0x10 - WDT real time interrupt
		B	PHANTOM 	; pvector addr offset 0x11 - XINT2
		B	PHANTOM		; Reserved pvector addr offset (0x12)
		B	PHANTOM		; Reserved pvector addr offset (0x13)
		B	PHANTOM		; Reserved pvector addr offset (0x14)
		B	PHANTOM		; Reserved pvector addr offset (0x15)
		B	PHANTOM		; Reserved pvector addr offset (0x16)
		B	PHANTOM		; Reserved pvector addr offset (0x17)
		B	PHANTOM		; Reserved pvector addr offset (0x18)
		B	PHANTOM		; Reserved pvector addr offset (0x19)
		B	PHANTOM		; Reserved pvector addr offset (0x1a)
		B	PHANTOM		; Reserved pvector addr offset (0x1b)
		B	PHANTOM		; Reserved pvector addr offset (0x1c)
		B	PHANTOM		; Reserved pvector addr offset (0x1d)
		B	PHANTOM		; Reserved pvector addr offset (0x1e)
		B	PHANTOM 	; pvector addr offset 0x1f - XINT3
		B	PHANTOM		; pvector addr offset 0x20 - PDP interrupt
		B	PHANTOM 	; pvector addr offset 0x21 - Full Compare 1  interrupt
		B	PHANTOM 	; pvector addr offset 0x22 -              2  interrupt
		B	PHANTOM 	; pvector addr offset 0x23 -              3 interrupt
		B	PHANTOM 	; pvector addr offset 0x24 - Simple Compare 1  interrupt
		B	PHANTOM 	; pvector addr offset 0x25 -                2  interrupt
		B	PHANTOM 	; pvector addr offset 0x26 -                3  interrupt
		B	PHANTOM 	; pvector addr offset 0x27 - T1 Period interrupt
		B	PHANTOM 	; pvector addr offset 0x28 -    Compare interrupt
		B	PHANTOM 	; pvector addr offset 0x29 -    Underflow interrupt
		B	PHANTOM 	; pvector addr offset 0x2a -    Overflow interrupt
		B	PHANTOM 	; pvector addr offset 0x2b - T2 Period interrupt
		B	PHANTOM 	; pvector addr offset 0x2c -    Compare interrupt
		B	PHANTOM 	; pvector addr offset 0x2d -    Underflow interrupt
		B	PHANTOM 	; pvector addr offset 0x2e -    Overflow interrupt
		B	PHANTOM 	; pvector addr offset 0x2f - T3 Period interrupt
		B	PHANTOM 	; pvector addr offset 0x30 -    Compare interrupt
		B	PHANTOM 	; pvector addr offset 0x31 -    Underflow interrupt
		B	PHANTOM 	; pvector addr offset 0x32 -    Overflow interrupt
		B	PHANTOM 	; pvector addr offset 0x33 - Capture 1 interrupt
		B	PHANTOM 	; pvector addr offset 0x34 - Capture 2 interrupt
		B	PHANTOM 	; pvector addr offset 0x35 - Capture 3 interrupt
		B	PHANTOM 	; pvector addr offset 0x36 - Capture 4 interrupt
;-----------------------------------------		

         .text
_c_int0:    
         SETC 	INTM
         CLRC 	SXM
         CLRC 	OVM
         CLRC 	CNF
         
         LDP 	#00E0H
         SPLK 	#81FEH,SCSR1    ;CLKIN=6M,CLKOUT=24M
         ;SPLK 	#87FEH,SCSR1    ;CLKIN=20M,CLKOUT=20M 
         SPLK	#0E8H,WDCR      ;WD disable    
               
         LDP 	#0
         LACC 	IFR
         SACL 	IFR
         SPLK 	#0001H,IMR      
         CLRC 	INTM

         CALL	ADINIT          ;Init. AD
         CALL	AD              ;Start AD
         
         MAR	*,AR1
         LAR	AR1,#flag
MAIN0:   BIT	*,14
         BCND   MAIN0,NTC
         mar	*,ar1
         LAR	AR1,#ADCHANN
         SPLK	#0,*
         CALL	FFT32         
         
MAIN:    NOP  

         B		MAIN         
         
INT1_ISR:
         SST	#0, ST0_CON1	; Auto page-0 DP addressing is used to 
		 SST	#1, ST1_CON1   ; save status registers to B2 DARAM.
         LDP	#DP_B12         ;380H/80H
		 SACL	ACCL_CON1	    ; save lower 16-bits of ACC
		 SACH	ACCH_CON1
		 SAR	AR0,AR0_CON1
		 SAR	AR1,AR1_CON1
		 SAR	AR2,AR2_CON1	

         LDP 	#00E0H
         LACC 	PVIR,1
         ADD 	#PVECTORS
         BACC

INT1RET:         
         LDP	#DP_B12
         LAR	AR0,AR0_CON1
         LAR	AR1,AR1_CON1
         LAR	AR2,AR2_CON1 
         LACC	ACCH_CON1,16
		 ADDS	ACCL_CON1
		 LDP	#0
		 LST	#1, ST1_CON1
		 LST	#0, ST0_CON1
		 CLRC	INTM
         RET
         
         
PHANTOM  B 		PHANTOM         

         END