?? lf2407regs.h
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;*************************************************************
; File Name : LF2407regs.h
; Originator : Texas Instrument-Chongqing University DSPs Lab.
; Description: LF2407 Peripheral Registers + other useful definitions
; Target : LF2407 DSK
; Author : Zhuo Qingfeng
; Last Update: 7-8-2001
;**************************************************************
;--------------------------------------------------------------
; On Chip Periperal Register Definitions
;--------------------------------------------------------------
;C2xx Core Registers
;~~~~~~~~~~~~~~~~~~~~
IMR .set 0004h ; Int Mask
GREG .set 0005h ; Global memory allocation
IFR .set 0006h ; Int Flag
ABRPT .set 01fh ; Analysis BreakPoint
WSGR .set 0FFFFh ; Wait State Control (IO space mapped)
;System Module Registers
;~~~~~~~~~~~~~~~~~~~~~~~
PIRQR0 .set 7010h ; Peripheral Interrupt Request Reg0
PIRQR1 .set 7011h ; Peripheral Interrupt Request Reg1
PIRQR2 .set 7012h ; Peripheral Interrupt Request Reg2
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge Reg0
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge Reg1
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge Reg2
SCSR1 .set 7018h ; System contr & stat 1
SCSR2 .set 7019h ; System contr & stat 2
DIN .set 701Ch ; Device Identification register
PVIR .set 701Eh ; Peripheral Interrupt Vector Register
;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
WDCNTR .set 7023h ; WD Counter reg
WDKEY .set 7025h ; WD Key reg
WDCR .set 7029h ; WD Control reg
;Serial Peripheral Interface (SPI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPI_CCR .set 7040h ; SPI Config Control Reg 1
SPI_CTL .set 7041h ; SPI Operation Control Reg 2
SPI_STS .set 7042h ; SPI Status Reg
SPI_BRR .set 7044h ; SPI Baud rate control reg
SPI_EMU .set 7046h ; SPI Emulation buffer reg
SPI_RXBUF .set 7047h ; SPI Serial Input buffer reg
SPI_TXBUF .set 7048h ; SPI Serial Output buffer reg
SPI_DAT .set 7049h ; SPI Serial Data reg
SPI_PC1 .set 704Dh ; SPI Port control reg1
SPI_PC2 .set 704Eh ; SPI Port control reg2
SPI_PRI .set 704Fh ; SPI Priority control reg
;Serial Communications Interface (SCI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SCICCR .set 7050h ; SCI Comms Control Reg
SCICTL1 .set 7051h ; SCI Control Reg 1
SCIHBAUD .set 7052h ; SCI Baud rate control
SCILBAUD .set 7053h ; SCI Baud rate control
SCICTL2 .set 7054h ; SCI Control Reg 2
SCIRXST .set 7055h ; SCI Receive status reg
SCIRXEMU .set 7056h ; SCI EMU data buffer
SCIRXBUF .set 7057h ; SCI Receive data buffer
SCITXBUF .set 7059h ; SCI Transmit data buffer
SCIPRI .set 705Fh ; SCI Priority control reg
; External interrupt configuration registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XINT1CR .set 7070h ; Int1 config.
XINT2CR .set 7071h ; Int2 config.
;Digital I/O Control Registers.
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
MCRA .set 7090h ; I/O Mux Control Reg A
MCRB .set 7092h ; I/O Mux Control Reg B
MCRC .set 7094h ; Output control C
IPSRA .set 7094h ; Input Status Reg A
IPSRB .set 7096h ; Input Status Reg B
PADATDIR .set 7098h ; I/O port A Data & Direction
PBDATDIR .set 709Ah ; I/O port B Data & Direction
PCDATDIR .set 709Ch ; I/O port C Data & Direction
PDDATDIR .set 709Eh ; I/O port D Data & Direction reg.
PEDATDIR .set 7095h ; I/O port D Data & Direction
PFDATDIR .set 7096h ; I/O port D Data & Direction
; ADC Register declarations
;--------------------------------------------------------------
ADCTRL1 .set 70A0h ; ADC Control reg 1
ADCTRL2 .set 70A1h ; ADC Control reg 2
MAXCONV .set 70A2h ; Maximum conversions in sequence
CHSELSEQ1 .set 70A3h ; Channel select fields: Results 3,2,1,0
CHSELSEQ2 .set 70A4h ; Channel select fields: Results 7,6,5,4
CHSELSEQ3 .set 70A5h ; Channel select fields: Results 11,10,9,8
CHSELSEQ4 .set 70A6h ; Channel select fields: Results 15,14,13,12
AUTO_SEQ_SR .set 70A7h ; Auto-sequence status Register
RESULT0 .set 70A8h ; Conversion result 0
RESULT1 .set 70A9h ; Conversion result 1
RESULT2 .set 70AAh ; Conversion result 2
RESULT3 .set 70ABh ; Conversion result 3
RESULT4 .set 70ACh ; Conversion result 4
RESULT5 .set 70ADh ; Conversion result 5
RESULT6 .set 70AEh ; Conversion result 6
RESULT7 .set 70AFh ; Conversion result 7
RESULT8 .set 70B0h ; Conversion result 8
RESULT9 .set 70B1h ; Conversion result 9
RESULT10 .set 70B2h ; Conversion result 10
RESULT11 .set 70B3h ; Conversion result 11
RESULT12 .set 70B4h ; Conversion result 12
RESULT13 .set 70B5h ; Conversion result 13
RESULT14 .set 70B6h ; Conversion result 14
RESULT15 .set 70B7h ; Conversion result 15
CALIBRATION .set 70B8h ; Calibration Register
; Controller Area Network(CAN) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAN_MDER .set 7100h ; Mailbox Direction/Enable Register
CAN_TCR .set 7101h ; Transmission Control Register
CAN_RCR .set 7102h ; Receive Control Register
CAN_MCR .set 7103h ; Master Control Register
CAN_BCR1 .set 7105h ; Bit Configuration Register 1
CAN_BCR2 .set 7104h ; Bit Configuration Register 2
CAN_ESR .set 7106h ; Error Status Register
CAN_GSR .set 7107h ; Global Status Register
CAN_CEC .set 7108h ; CAN Error Counter Register
CAN_IFR .set 7109h ; CAN Interrupt Flag Register
CAN_IMR .set 710Ah ; CAN Interrupt Mask Register
CAN_LAM0_H .set 710Bh ; Local Acceptance Mask register 0 High Word
CAN_LAM0_L .set 710Ch ; Local Acceptance Mask register 0 Low Word
CAN_LAM1_H .set 710Dh ; Local Acceptance Mask register 1 High Word
CAN_LAM1_L .set 710Eh ; Local Acceptance Mask register 1 Low Word
CAN_MSGID0L .set 7200h ; Can Message Identifier for Mailbox 0 Low Word
CAN_MSGID0H .set 7201h ; Can Message Identifier for Mailbox 0 High Word
CAN_MSGCTRL0 .set 7202h ; Can Message Control Field for Mailbox 0
CAN_MBX0A .set 7204h ; Mailbox 0 A
CAN_MBX0B .set 7205h ; Mailbox 0 B
CAN_MBX0C .set 7206h ; Mailbox 0 C
CAN_MBX0D .set 7207h ; Mailbox 0 D
CAN_MSGID1L .set 7208h ; Can Message Identifier for Mailbox 1 Low Word
CAN_MSGID1H .set 7209h ; Can Message Identifier for Mailbox 1 High Word
CAN_MSGCTRL1 .set 720Ah ; Can Message Control Field for Mailbox 1
CAN_MBX1A .set 720Ch ; Mailbox 1 A
CAN_MBX1B .set 720Dh ; Mailbox 1 B
CAN_MBX1C .set 720Eh ; Mailbox 1 C
CAN_MBX1D .set 720Fh ; Mailbox 1 D
CAN_MSGID2L .set 7210h ; Can Message Identifier for Mailbox 2 Low Word
CAN_MSGID2H .set 7211h ; Can Message Identifier for Mailbox 2 High Word
CAN_MSGCTRL2 .set 7212h ; Can Message Control Field for Mailbox 2
CAN_MBX2A .set 7214h ; Mailbox 2 A
CAN_MBX2B .set 7215h ; Mailbox 2 B
CAN_MBX2C .set 7216h ; Mailbox 2 C
CAN_MBX2D .set 7217h ; Mailbox 2 D
CAN_MSGID3L .set 7218h ; Can Message Identifier for Mailbox 3 Low Word
CAN_MSGID3H .set 7219h ; Can Message Identifier for Mailbox 3 High Word
CAN_MSGCTRL3 .set 721Ah ; Can Message Control Field for Mailbox 3
CAN_MBX3A .set 721Ch ; Mailbox 3 A
CAN_MBX3B .set 721Dh ; Mailbox 3 B
CAN_MBX3C .set 721Eh ; Mailbox 3 C
CAN_MBX3D .set 721Fh ; Mailbox 3 D
CAN_MSGID4L .set 7220h ; Can Message Identifier for Mailbox 4 Low Word
CAN_MSGID4H .set 7221h ; Can Message Identifier for Mailbox 4 High Word
CAN_MSGCTRL4 .set 7222h ; Can Message Control Field for Mailbox 4
CAN_MBX4A .set 7224h ; Mailbox 4 A
CAN_MBX4B .set 7225h ; Mailbox 4 B
CAN_MBX4C .set 7226h ; Mailbox 4 C
CAN_MBX4D .set 7227h ; Mailbox 4 D
CAN_MSGID5L .set 7228h ; Can Message Identifier for Mailbox 5 Low Word
CAN_MSGID5H .set 7229h ; Can Message Identifier for Mailbox 5 High Word
CAN_MSGCTRL5 .set 722Ah ; Can Message Control Field for Mailbox 5
CAN_MBX5A .set 722Ch ; Mailbox 5 A
CAN_MBX5B .set 722Dh ; Mailbox 5 B
CAN_MBX5C .set 722Eh ; Mailbox 5 C
CAN_MBX5D .set 722Fh ; Mailbox 5 D
;Event Manager (EV)/Event Manager A (EVA) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONA .set 7400h ; General Timer Control
T1CNT .set 7401h ; T1 Counter
T1CMP .set 7402h ; T1 Compare Value
T1PER .set 7403h ; T1 Period
T1CON .set 7404h ; T1 Control
T2CNT .set 7405h ; T2 Counter
T2CMP .set 7406h ; T2 Compare Value
T2PER .set 7407h ; T2 Period
T2CON .set 7408h ; T2 Control
COMCONA .set 7411h ; Compare Control
ACTRA .set 7413h ; Compare Output Action Control
DBTCONA .set 7415h ; Dead Band Control
CMPR1 .set 7417h ; Compare Value 1
CMPR2 .set 7418h ; Compare Value 2
CMPR3 .set 7419h ; Compare Value 3
CAPCONA .set 7420h ; Capture Control
CAPFIFOA .set 7422h ; Capture FIFO A Status Register
FIFO1 .set 7423h ; Capture 1 FIFO Top
FIFO2 .set 7424h ; Capture 2 FIFO Top
FIFO3 .set 7425h ; Capture 3 FIFO Top
FIFOBT1 .set 7427h ; Capture 1 FIFO Bottom
FIFOBT2 .set 7428h ; Capture 2 FIFO Bottom
FIFOBT3 .set 7429h ; Capture 3 FIFO Bottom
EVAIMRA .set 742ch ; EVA Interrupt Mask Register A
EVAIMRB .set 742dh ; EVA Interrupt Mask Register B
EVAIMRC .set 742eh ; EVA Interrupt Mask Register C
EVAIFRA .set 742Fh ; EVA Interrupt Flag Register A
EVAIFRB .set 7430h ; EVA Interrupt Flag Register A
EVAIFRC .set 7431h ; EVA Interrupt Flag Register A
;Event Manager B (EVB) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONB .set 7500h ; General Timer Control
T3CNT .set 7501h ; T1 Counter
T3CMP .set 7502h ; T1 Comp Value
T3PER .set 7503h ; T1 Period
T3CON .set 7504h ; T1 Control
T4CNT .set 7505h ; T2 Counter
T4CMP .set 7506h ; T2 Comp Value
T4PER .set 7507h ; T2 Period
T4CON .set 7508h ; T2 Control
COMCONB .set 7511h ; Compare Control
ACTRB .set 7513h ; Compare Output Action Control
DBTCONB .set 7515h ; Dead Band Control
CMPR4 .set 7517h ; Comp Value 4
CMPR5 .set 7518h ; Comp Value 5
CMPR6 .set 7519h ; Comp Value 6
CAPCONB .set 7520h ; Capture Control
CAPFIFOB .set 7522h ; Capture FIFO4-6 Status
FIFO4B .set 7523h ; Capture 4 FIFO Top
FIFO5B .set 7524h ; Capture 5 FIFO Top
FIFO6B .set 7525h ; Capture 6 FIFO Top
FIFOBT4B .set 7527h ; Capture 4 FIFO Bottom
FIFOBT5B .set 7528h ; Capture 5 FIFO Bottom
FIFOBT6B .set 7529h ; Capture 6 FIFO Bottom
EVBIMRA .set 752ch ; Group A Int Mask
EVBIMRB .set 752dh ; Group B Int Mask
EVBIMRC .set 752eh ; Group C Int Mask
EVBIFRA .set 752fh ; Group A Int Flag
EVBIFRB .set 7530h ; Group B Int Flag
EVBIFRC .set 7531h ; Group C Int Flag
;-----------------------------------------------------------------------------
; Constant defines
;-----------------------------------------------------------------------------
;Data Space
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B2_SADDR .set 0060h ;Block B2 start address
B2_EADDR .set 007Fh ;Block B2 end address
B0_SADDR .set 0200h ;Block B0 start address
B0_EADDR .set 02FFh ;Block B0 end address
B1_SADDR .set 0300h ;Block B1 start address
B1_EADDR .set 03FFh ;Block B1 end address
SARAM .set 0800h ;SARAM start address(0800h-0FFFh)
EXTDATA .set 8000h ;External Data Space start address
;Frequently Used Data Pages
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
DP_B2 .set 0 ;Page 0 of data space
DP_B01 .set 4 ;Page 4 of B0(200H/80H)
DP_B02 .set 5 ;Page 5 of B0(280H/80H)
DP_B11 .set 6 ;Page 6 of B1(300H/80H)
DP_B12 .set 7 ;Page 7 of B1(380H/80H)
DP_SARAM1 .set 16 ;Page 16 of SARAM(800H/80H)
DP_PF1 .set 224 ;Page 1 of peripheral file (7000h/80h)(0XE0)
DP_PF2 .set 225 ;Page 2 of peripheral file (7080h/80h)(0XE1)
DP_PF3 .set 226 ;Page 3 of peripheral file (7100h/80h)(0XE2)
DP_EVA .set 232 ;EVA reg file (7400h/80h)(0XE8)
DP_EVB .set 234 ;EVB reg file (7500h/80h)(0XEA)
DP_EXT1 .set 256 ;The first block of ext. memory (8000H/80H)
;Bit codes for Test bit instruction (BIT)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
BIT15 .set 0000h ;Bit Code for 15
BIT14 .set 0001h ;Bit Code for 14
BIT13 .set 0002h ;Bit Code for 13
BIT12 .set 0003h ;Bit Code for 12
BIT11 .set 0004h ;Bit Code for 11
BIT10 .set 0005h ;Bit Code for 10
BIT9 .set 0006h ;Bit Code for 9
BIT8 .set 0007h ;Bit Code for 8
BIT7 .set 0008h ;Bit Code for 7
BIT6 .set 0009h ;Bit Code for 6
BIT5 .set 000Ah ;Bit Code for 5
BIT4 .set 000Bh ;Bit Code for 4
BIT3 .set 000Ch ;Bit Code for 3
BIT2 .set 000Dh ;Bit Code for 2
BIT1 .set 000Eh ;Bit Code for 1
BIT0 .set 000Fh ;Bit Code for 0
; Used by the SBIT0 & SBIT1 Macro
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B15_MSK .set 8000h ;Bit Mask for 15
B14_MSK .set 4000h ;Bit Mask for 14
B13_MSK .set 2000h ;Bit Mask for 13
B12_MSK .set 1000h ;Bit Mask for 12
B11_MSK .set 0800h ;Bit Mask for 11
B10_MSK .set 0400h ;Bit Mask for 10
B9_MSK .set 0200h ;Bit Mask for 9
B8_MSK .set 0100h ;Bit Mask for 8
B7_MSK .set 0080h ;Bit Mask for 7
B6_MSK .set 0040h ;Bit Mask for 6
B5_MSK .set 0020h ;Bit Mask for 5
B4_MSK .set 0010h ;Bit Mask for 4
B3_MSK .set 0008h ;Bit Mask for 3
B2_MSK .set 0004h ;Bit Mask for 2
B1_MSK .set 0002h ;Bit Mask for 1
B0_MSK .set 0001h ;Bit Mask for 0
;Watchdog timer reset string
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wd_rst_1 .set 055h
wd_rst_2 .set 0aah
;-----------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------
SBIT0 .macro DMA,MASK ; Clear bit Macro
LACC DMA
AND #(0FFFFh-MASK)
SACL DMA
.endm
SBIT1 .macro DMA,MASK ; Set bit Macro
LACC DMA
OR #MASK
SACL DMA
.endm
KICK_DOG .macro ;Watchdog reset macro
LDP #WD_KEY>>7
SPLK #05555h,WD_KEY
SPLK #0AAAAh,WD_KEY
.endm
POINT_PG0 .macro
LDP #00h
.endm
POINT_B0 .macro
LDP #04h
.endm
POINT_PF1 .macro
LDP #0E0h
.endm
POINT_PF2 .macro
LDP #0E1h
.endm
POINT_EV .macro
LDP #0E8h
.endm
;-----------------------------------------------------------------------
; User Defines
;-----------------------------------------------------------------------
.def lcdcmd,lcddata,lcdzktab,flag,KEYCOUNT,KEYTMP,KEYFLAG
.bss flag,1 ;flag.0--LCD,flag.1-AD
.bss lcdcmd,1
.bss lcddata,1
.bss lcdzktab,1
.bss ST0_CON1,1
.bss ST1_CON1,1
.bss ST0_CON2,1
.bss ST1_CON2,1
.bss KEYCOUNT,1
.bss KEYTMP,1
.bss KEYFLAG,1
;------------Block B12--------------
ACCL_CON1 .usect ".context",1
ACCH_CON1 .usect ".context",1
AR0_CON1 .usect ".context",1
AR1_CON1 .usect ".context",1
AR2_CON1 .usect ".context",1
ACC_CONL2 .usect ".context",1
ACC_CONH2 .usect ".context",1
;Comment:Timer1--KEY&LCD,Timer2--CAP,Timer3--PWM,Timer4--AD?? 快捷鍵說明
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