?? led_shift.lis
字號:
0002 INT_MSK2_SOF: equ 02h ; MASK: enable/disable I2C interrupt
0001 INT_MSK2_BUS_RESET: equ 01h ; MASK: enable/disable SW interrupt
0000
00E0 INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
0080 INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
0040 INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
0020 INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
0004 INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
0002 INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
0001 INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
0000
00E1 INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
0008 INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
0004 INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
0002 INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
0001 INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
0000
00E2 INT_VC: equ E2h ; Interrupt vector register (RC)
00E3 RES_WDT: equ E3h ; Watch Dog Timer Register (W)
0000
0000 ; DECIMATOR Control Registers
00E4 DEC_DH: equ E4h ; Data High Register (RW)
00E5 DEC_DL: equ E5h ; Data Low Register (RW)
00E6 DEC_CR0: equ E6h ; Data Control Register 0 (RW)
00E7 DEC_CR1: equ E7h ; Data Control Register 1 (RW)
0000
0000 ;------------------------------------------------------
0000 ; MAC Registers
0000 ;------------------------------------------------------
0000
00E8 MUL0_X: equ E8h ; Multiply Input X Register (W)
00E9 MUL0_Y: equ E9h ; Multiply Input Y Register (W)
00EA MUL0_DH: equ EAh ; Multiply Result High Byte Register (R)
00EB MUL0_DL: equ EBh ; Multiply Result Low Byte Register (R)
0000
00EC ACC0_DR1: equ ECh ; Accumulator Data Register 1 (RW)
00ED ACC0_DR0: equ EDh ; Accumulator Data Register 0 (RW)
00EE ACC0_DR3: equ EEh ; Accumulator Data Register 3 (RW)
00EF ACC0_DR2: equ EFh ; Accumulator Data Register 2 (RW)
0000
0000 ;------------------------------------------------------
0000 ; System Status and Control Registers
0000 ;
0000 ; Note: The following registers are mapped into both
0000 ; register bank 0 AND register bank 1.
0000 ;------------------------------------------------------
00F7 CPU_F: equ F7h ; CPU Flag Register Access (RO)
0000 ; Use FLAG_ masks defined at top of file
0000
00FD DAC_D: equ FDh ; DAC Data Register (RW)
0000
00FE CPU_SCR1: equ FEh ; CPU Status and Control Register #1 (#)
0080 CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
0010 CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
0008 CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
0004 CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
0001 CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
0000
00FF CPU_SCR0: equ FFh ; CPU Status and Control Register #2 (#)
0080 CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
0020 CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
0010 CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
0008 CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
0001 CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 1
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
0001 PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
0002 PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
0003 PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
0000
0000 ; Port 1
0004 PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
0005 PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
0006 PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
0007 PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
0000
0000 ; Port 2
0008 PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
0009 PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
000A PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
000B PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
0000
0000 ; Port 3
000C PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
000D PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
000E PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
000F PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
0000
0000 ; Port 4
0010 PRT4DM0: equ 10h ; Port 4 Drive Mode 0 (RW)
0011 PRT4DM1: equ 11h ; Port 4 Drive Mode 1 (RW)
0012 PRT4IC0: equ 12h ; Port 4 Interrupt Control 0 (RW)
0013 PRT4IC1: equ 13h ; Port 4 Interrupt Control 1 (RW)
0000
0000 ; Port 5
0014 PRT5DM0: equ 14h ; Port 5 Drive Mode 0 (RW)
0015 PRT5DM1: equ 15h ; Port 5 Drive Mode 1 (RW)
0016 PRT5IC0: equ 16h ; Port 5 Interrupt Control 0 (RW)
0017 PRT5IC1: equ 17h ; Port 5 Interrupt Control 1 (RW)
0000
0000 ; Port 7
001C PRT7DM0: equ 1Ch ; Port 7 Drive Mode 0 (RW)
001D PRT7DM1: equ 1Dh ; Port 7 Drive Mode 1 (RW)
001E PRT7IC0: equ 1Eh ; Port 7 Interrupt Control 0 (RW)
001F PRT7IC1: equ 1Fh ; Port 7 Interrupt Control 1 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00FN: equ 20h ; Function Register (RW)
0021 DBB00IN: equ 21h ; Input Register (RW)
0022 DBB00OU: equ 22h ; Output Register (RW)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01FN: equ 24h ; Function Register (RW)
0025 DBB01IN: equ 25h ; Input Register (RW)
0026 DBB01OU: equ 26h ; Output Register (RW)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02FN: equ 28h ; Function Register (RW)
0029 DCB02IN: equ 29h ; Input Register (RW)
002A DCB02OU: equ 2Ah ; Output Register (RW)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03FN: equ 2Ch ; Function Register (RW)
002D DCB03IN: equ 2Dh ; Input Register (RW)
002E DCB03OU: equ 2Eh ; Output Register (RW)
0000
0000 ;------------------------------------------------
0000 ; PMA Write and Read Registers
0000 ;------------------------------------------------
0000
0040 PMA0_WA: equ 40h ; PMA Write Pointer Register (RW)
0041 PMA1_WA: equ 41h ; PMA Write Pointer Register (RW)
0042 PMA2_WA: equ 42h ; PMA Write Pointer Register (RW)
0043 PMA3_WA: equ 43h ; PMA Write Pointer Register (RW)
0044 PMA4_WA: equ 44h ; PMA Write Pointer Register (RW)
0045 PMA5_WA: equ 45h ; PMA Write Pointer Register (RW)
0046 PMA6_WA: equ 46h ; PMA Write Pointer Register (RW)
0047 PMA7_WA: equ 47h ; PMA Write Pointer Register (RW)
0000
0050 PMA0_RA: equ 50h ; PMA Read Pointer Register (RW)
0051 PMA1_RA: equ 51h ; PMA Read Pointer Register (RW)
0052 PMA2_RA: equ 52h ; PMA Read Pointer Register (RW)
0053 PMA3_RA: equ 53h ; PMA Read Pointer Register (RW)
0054 PMA4_RA: equ 54h ; PMA Read Pointer Register (RW)
0055 PMA5_RA: equ 55h ; PMA Read Pointer Register (RW)
0056 PMA6_RA: equ 56h ; PMA Read Pointer Register (RW)
0057 PMA7_RA: equ 57h ; PMA Read Pointer Register (RW)
0000
0000
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ; Note: Also see this address range in Bank 0.
0000 ;------------------------------------------------
0000
0060 CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
000C CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
0003 CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
0000
0061 CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
0040 CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
0038 CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
0007 CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
0000
0062 ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
0080 ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
0020 ABF_CR0_ABUF1EN: equ 20h ; MASK: Enable ACol 1 analog buffer (P0[5])
0008 ABF_CR0_ABUF0EN: equ 08h ; MASK: Enable ACol 0 analog buffer (P0[3])
0002 ABF_CR0_BYPASS: equ 02h ; MASK: Bypass the analog buffers
0001 ABF_CR0_PWR: equ 01h ; MASK: High power mode on all analog buffers
0000
0063 AMD_CR0: equ 63h ; Analog Modulator Control Register 0 (RW)
0007 AMD_CR0_AMOD0: equ 07h ; MASK: Modulation source for analog column 1
0000
0064 CMP_GO_EN: equ 64h ; Comparator Bus 0/1 To Global Out Enable (RW)
0080 CMP_GO_EN_GOO5: equ 80h ; MASK: Selected Col 1 signal to GOO5
0040 CMP_GO_EN_GOO1: equ 40h ; MASK: Selected Col 1 signal to GOO1
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