?? usbfs_1int.lis
字號:
0000
0000 ; ------------------------------------------------------------------------------
0000 ; The following defines are depricated. Left here for compatibility.
0056 EP0_CR0: equ 56h ; Endpoint 0 Control Register 0 (#)
0080 EP0_CR0_SETUP_RCVD: equ 80h ; MASK: Setup received (RC)
0040 EP0_CR0_IN_RCVD: equ 40h ; MASK: IN received (RC)
0020 EP0_CR0_OUT_RCVD: equ 20h ; MASK: OUT received (RC)
0010 EP0_CR0_ACKD: equ 10h ; MASK: Acked transaction (RC)
000F EP0_CR0_MODE: equ 0Fh ; MASK: Mode response for endpoint (RW)
0000 ; ------------------------------------------------------------------------------
0000
0057 EP0_CNT: equ 57h ; Endpoint 0 Count Register (#)
0080 EP0_CNT_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
0040 EP0_CNT_DATA_VALID: equ 40h ; MASK: read error status on rx data (RC)
000F EP0_CNT_BYTE_CNT: equ 0Fh ; MASK: MSB of 9-bit count value (RW)
0000
0058 EP0_DR0: equ 58h ; Endpoint 0 Data Register 0 (RW)
0059 EP0_DR1: equ 59h ; Endpoint 0 Data Register 1 (RW)
005A EP0_DR2: equ 5Ah ; Endpoint 0 Data Register 2 (RW)
005B EP0_DR3: equ 5Bh ; Endpoint 0 Data Register 3 (RW)
005C EP0_DR4: equ 5Ch ; Endpoint 0 Data Register 4 (RW)
005D EP0_DR5: equ 5Dh ; Endpoint 0 Data Register 5 (RW)
005E EP0_DR6: equ 5Eh ; Endpoint 0 Data Register 6 (RW)
005F EP0_DR7: equ 5Fh ; Endpoint 0 Data Register 7 (RW)
0000
0000 ;-------------------------------------
0000 ; Analog Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0061 AMUXCFG: equ 61h ; Analog Mux Bus Configuration Register (RW)
0080 AMUXCFG_BCOL0_MUX: equ 80h ; MASK: select AMuxBusB for Col1 input (RW)
0040 AMUXCFG_ACOL0_MUX: equ 40h ; MASK: select AMuxBusA for Col0 input (RW)
0030 AMUXCFG_INTCAP: equ 30h ; MASK: select pins for static operation (RW)
000E AMUXCFG_MUXCLK: equ 0Eh ; MASK: select precharge clock source (RW)
0001 AMUXCFG_EN: equ 01h ; MASK: enable/disable MUXCLK (RW)
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
0007 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
0003 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0002 CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
0001 CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
0000
0065 ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
0070 ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
0008 ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
0006 ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
0001 ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
0000
0066 CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
0020 CMP_CR1_CLDIS1: equ 20h ; MASK: Column 1 comparator bus synch
0010 CMP_CR1_CLDIS0: equ 10h ; MASK: Column 0 comparator bus synch
0002 CMP_CR1_CLDIX1: equ 02h ; MASK: Column 1 comparator bus synch
0001 CMP_CR1_CLDIX0: equ 01h ; MASK: Column 0 comparator bus synch
0000
0000 ;-----------------------------------------------
0000 ; Global General Purpose Data Registers
0000 ;-----------------------------------------------
006C TMP_DR0: equ 6Ch ; Temporary Data Register 0 (RW)
006D TMP_DR1: equ 6Dh ; Temporary Data Register 1 (RW)
006E TMP_DR2: equ 6Eh ; Temporary Data Register 2 (RW)
006F TMP_DR3: equ 6Fh ; Temporary Data Register 3 (RW)
0000
0000 ;---------------------------------------------------
0000 ; Analog PSoC block Registers
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;---------------------------------------------------
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 0
0070 ACB00CR3: equ 70h ; Control register 3 (RW)
0071 ACB00CR0: equ 71h ; Control register 0 (RW)
0072 ACB00CR1: equ 72h ; Control register 1 (RW)
0073 ACB00CR2: equ 73h ; Control register 2 (RW)
0000
0000 ; Continuous Time PSoC block Type B Row 0 Col 1
0074 ACB01CR3: equ 74h ; Control register 3 (RW)
0075 ACB01CR0: equ 75h ; Control register 0 (RW)
0076 ACB01CR1: equ 76h ; Control register 1 (RW)
0077 ACB01CR2: equ 77h ; Control register 2 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 1 Col 0
0080 ASC10CR0: equ 80h ; Control register 0 (RW)
0081 ASC10CR1: equ 81h ; Control register 1 (RW)
0082 ASC10CR2: equ 82h ; Control register 2 (RW)
0083 ASC10CR3: equ 83h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 1 Col 1
0084 ASD11CR0: equ 84h ; Control register 0 (RW)
0085 ASD11CR1: equ 85h ; Control register 1 (RW)
0086 ASD11CR2: equ 86h ; Control register 2 (RW)
0087 ASD11CR3: equ 87h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType D Row 2 Col 0
0090 ASD20CR0: equ 90h ; Control register 0 (RW)
0091 ASD20CR1: equ 91h ; Control register 1 (RW)
0092 ASD20CR2: equ 92h ; Control register 2 (RW)
0093 ASD20CR3: equ 93h ; Control register 3 (RW)
0000
0000 ; Switched Cap PSoC blockType C Row 2 Col 1
0094 ASC21CR0: equ 94h ; Control register 0 (RW)
0095 ASC21CR1: equ 95h ; Control register 1 (RW)
0096 ASC21CR2: equ 96h ; Control register 2 (RW)
0097 ASC21CR3: equ 97h ; Control register 3 (RW)
0000
0000 ;------------------------------------------------
0000 ; Row Digital Interconnects
0000 ;
0000 ; Note: the following registers are mapped into
0000 ; both register bank 0 AND register bank 1.
0000 ;------------------------------------------------
0000
00B0 RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
00B1 RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
00B2 RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
00B3 RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
00B4 RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
00B5 RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
00B6 RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
0000
0000 ;-----------------------------------------------
0000 ; Ram Page Pointers
0000 ;-----------------------------------------------
00D0 CUR_PP: equ D0h ; Current Page Pointer
00D1 STK_PP: equ D1h ; Stack Page Pointer
00D3 IDX_PP: equ D3h ; Index Page Pointer
00D4 MVR_PP: equ D4h ; MVI Read Page Pointer
00D5 MVW_PP: equ D5h ; MVI Write Page Pointer
0000
0000 ;------------------------------------------------
0000 ; I2C Configuration Registers
0000 ;------------------------------------------------
00D6 I2C_CFG: equ D6h ; I2C Configuration Register (RW)
0040 I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
0020 I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
0010 I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
0000 I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
0004 I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
0008 I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
000C I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
000C I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
0002 I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
0001 I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
0000
00D7 I2C_SCR: equ D7h ; I2C Status and Control Register (#)
0080 I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
0040 I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
0020 I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
0010 I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
0008 I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
0004 I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
0002 I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
0001 I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
0000
00D8 I2C_DR: equ D8h ; I2C Data Register (RW)
0000
00D9 I2C_MSCR: equ D9h ; I2C Master Status and Control Register (#)
0008 I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
0004 I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
0002 I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
0001 I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
0000
0000 ;------------------------------------------------
0000 ; System and Global Resource Registers
0000 ;------------------------------------------------
00DA INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
0000 ; Use INT_MSK0 bit field masks
00DB INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
0000 ; Use INT_MSK1 bit field masks
00DC INT_CLR2: equ DCh ; Interrupt Clear Register 2 (RW)
0000 ; Use INT_MSK2 bit field masks
00DD INT_CLR3: equ DDh ; Interrupt Clear Register 3 (RW)
0000 ; Use INT_MSK3 bit field masks
0000
00DE INT_MSK3: equ DEh ; I2C and Software Mask Register (RW)
0080 INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
0001 INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
0000
00DF INT_MSK2: equ DFh ; USB Mask Register (RW)
0080 INT_MSK2_WAKEUP: equ 80h ; MASK: enable/disable I2C interrupt
0040 INT_MSK2_EP4: equ 40h ; MASK: enable/disable SW interrupt
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