?? psocconfig.lis
字號:
0000 ; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
0000 ;
0000 ;==========================================================================
0000 ; PSoCConfig.asm
0000 ; @PSOC_VERSION
0000 ;
0000 ; Version: 0.85
0000 ; Revised: June 22, 2004
0000 ; Copyright Cypress MicroSystems 2000-2004. All Rights Reserved.
0000 ;
0000 ; This file is generated by the Device Editor on Application Generation.
0000 ; It contains code which loads the configuration data table generated in
0000 ; the file PSoCConfigTBL.asm
0000 ;
0000 ; DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
0000 ; Edits to this file will not be preserved.
0000 ;==========================================================================
0000 ;
00C0 FLAG_PGMODE_MASK: equ C0h ; Paging control for > 256 bytes of RAM
0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
00C0 FLAG_PGMODE_3: equ C0h ; Direct to CUR_PP page, indexed to STK_PP page
0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
00C0 FLAG_PGMODE_11b: equ C0h ; Same as PGMODE_3
0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
0008 FLAG_SUPER: equ 08h ; Supervisor Mode
0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000 ; Port 7
001C PRT7DR: equ 1Ch ; Port 7 Data Register (RW)
001D PRT7IE: equ 1Dh ; Port 7 Interrupt Enable Register (RW)
001E PRT7GS: equ 1Eh ; Port 7 Global Select Register (RW)
001F PRT7DM2: equ 1Fh ; Port 7 Drive Mode 2 (RW)
0000
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ;------------------------------------------------
0000 ; PMA Data Registers
0000 ;------------------------------------------------
0000
0040 PMA0_DR: equ 40h ; PMA Data Register (RW)
0041 PMA1_DR: equ 41h ; PMA Data Register (RW)
0042 PMA2_DR: equ 42h ; PMA Data Register (RW)
0043 PMA3_DR: equ 43h ; PMA Data Register (RW)
0044 PMA4_DR: equ 44h ; PMA Data Register (RW)
0045 PMA5_DR: equ 45h ; PMA Data Register (RW)
0046 PMA6_DR: equ 46h ; PMA Data Register (RW)
0047 PMA7_DR: equ 47h ; PMA Data Register (RW)
0000
0000 ;------------------------------------------------
0000 ; USB Registers
0000 ;------------------------------------------------
0000
0048 USB_SOF0: equ 48h ; SOF Frame Number LSB(7:0) (R)
0049 USB_SOF1: equ 49h ; SOF Frame Number MSB(10:8) (R)
0000
004A USB_CR0: equ 4Ah ; USB Control Register 0 (RW)
0080 USB_CR0_ENABLE: equ 80h ; MASK: enable/disable USB SIE (RW)
007F USB_CR0_DEVICE_ADDR: equ 7Fh ; MASK: USB Device Address (RW)
0000
004B USBIO_CR0: equ 4Bh ; USB IO Control Register 0 (#)
0080 USBIO_CR0_TEN: equ 80h ; MASK: enable/disable manual tx on D+ D-(RW)
0040 USBIO_CR0_TSE0: equ 40h ; MASK: transmit a single ended 0 (RW)
0020 USBIO_CR0_TD: equ 20h ; MASK: transmit J or K state on Bus (RW)
0001 USBIO_CR0_RD: equ 01h ; MASK: read state of differential rx (R)
0000
004C USBIO_CR1: equ 4Ch ; USB IO Control Register 0 (RW)
0080 USBIO_CR1_IOMODE: equ 80h ; MASK: select Bit Bang Mode/USB Mode (RW)
0040 USBIO_CR1_DRIVE_MODE: equ 40h ; MASK: select CMOS mode/Open Drain mode (RW)
0020 USBIO_CR1_DPI: equ 20h ; MASK: drive D+ high/low (RW)
0010 USBIO_CR1_DMI: equ 10h ; MASK: drive D- high/low (RW)
0008 USBIO_CR1_PS2PUEN: equ 08h ; MASK: enable/disable 5K Pullup on D+/D-(RW)
0004 USBIO_CR1_USBPUEN: equ 04h ; MASK: enable/disable USB Pullup on D+ (RW)
0002 USBIO_CR1_DPO: equ 02h ; MASK: read D+ pin (R)
0001 USBIO_CR1_DMO: equ 01h ; MASK: read D- pin (R)
0000
0000
0000 ;------------------------------------------------
0000 ; USB Endpoint Registers
0000 ;------------------------------------------------
0000
004E EP1_CNT1: equ 4Eh ; Endpoint 1 Count Register 1 (#)
0080 EP1_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
0040 EP1_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
0001 EP1_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
0000
004F EP1_CNT: equ 4Fh ; Endpoint 1 Count Register 0 (RW)
0000
0050 EP2_CNT1: equ 50h ; Endpoint 2 Count Register 1 (#)
0080 EP2_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
0040 EP2_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
0001 EP2_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
0000
0051 EP2_CNT: equ 51h ; Endpoint 2 Count Register 0 (RW)
0000
0052 EP3_CNT1: equ 52h ; Endpoint 3 Count Register 1 (#)
0080 EP3_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
0040 EP3_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
0001 EP3_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
0000
0053 EP3_CNT: equ 53h ; Endpoint 3 Count Register 0 (RW)
0000
0054 EP4_CNT1: equ 54h ; Endpoint 4 Count Register 1 (#)
0080 EP4_CNT1_DATA_TOGGLE: equ 80h ; MASK: select data toggle 1/0 (RW)
0040 EP4_CNT1_DATA_VALID: equ 40h ; MASK: read error status on rx data (R)
0001 EP4_CNT1_CNT_MSB: equ 01h ; MASK: MSB of 9-bit count value (RW)
0000
0055 EP4_CNT: equ 55h ; Endpoint 4 Count Register 0 (RW)
0000
0056 EP0_CR: equ 56h ; Endpoint 0 Control Register 0 (#)
0080 EP0_CR_SETUP_RCVD: equ 80h ; MASK: Setup received (RC)
0040 EP0_CR_IN_RCVD: equ 40h ; MASK: IN received (RC)
0020 EP0_CR_OUT_RCVD: equ 20h ; MASK: OUT received (RC)
0010 EP0_CR_ACKD: equ 10h ; MASK: Acked transaction (RC)
000F EP0_CR_MODE: equ 0Fh ; MASK: Mode response for endpoint (RW)
0000
0000 ; ------------------------------------------------------------------------------
0000 ; The following defines are depricated. Left here for compatibility.
0056 EP0_CR0: equ 56h ; Endpoint 0 Control Register 0 (#)
0080 EP0_CR0_SETUP_RCVD: equ 80h ; MASK: Setup received (RC)
0040 EP0_CR0_IN_RCVD: equ 40h ; MASK: IN received (RC)
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