?? psocconfig.lis
字號:
0000
0065 CMP_GO_EN1: equ 65h ; Comparator Bus 2/3 To Global Out Enable (RW)
0080 CMP_GO_EN1_GOO7: equ 80h ; MASK: Selected Col 3 signal to GOO5
0040 CMP_GO_EN1_GOO3: equ 40h ; MASK: Selected Col 3 signal to GOO1
0030 CMP_GO_EN1_SEL3: equ 30h ; MASK: Column 3 Signal Select
0008 CMP_GO_EN1_GOO6: equ 08h ; MASK: Selected Col 2 signal to GOO4
0004 CMP_GO_EN1_GOO2: equ 04h ; MASK: Selected Col 2 signal to GOO0
0003 CMP_GO_EN1_SEL2: equ 03h ; MASK: Column 2 Signal Select
0000
0066 AMD_CR1: equ 66h ; Analog Modulator Control Register 1 (RW)
0007 AMD_CR1_AMOD1: equ 07h ; MASK: Modulation ctrl for analog column 1
0000
0067 ALT_CR0: equ 67h ; Analog Look Up Table (LUT) Register 0 (RW)
00F0 ALT_CR0_LUT1: equ F0h ; MASK: Look up table 1 selection
000F ALT_CR0_LUT0: equ 0Fh ; MASK: Look up table 0 selection
0000
0000
0000 ;------------------------------------------------
0000 ; USB Registers
0000 ;------------------------------------------------
0000
00C1 USB_CR1: equ C1h ; USB Control Register 1 (#)
0004 USB_CR1_BUS_ACTIVITY: equ 04h ; MASK: monitors activity on USB bus (RC)
0002 USB_CR1_ENABLE_LOCK: equ 02h ; MASK: enable/disable auto lock of osc (RW)
0001 USB_CR1_REG_ENABLE: equ 01h ; MASK: set mode to reg. on/pass thru (RW)
0000
00C4 EP1_CR0: equ C4h ; EP1 Control Register 0 (#)
0080 EP1_CR0_STALL: equ 80h ; MASK: enable/disable stall (RW)
0020 EP1_CR0_NAK_INT_EN: equ 20h ; MASK: enable/disable NAK interrupts (RW)
0010 EP1_CR0_ACKD: equ 10h ; MASK: set when acked transaction occurs(RC)
000F EP1_CR0_MODE: equ 0Fh ; MASK: mode control for endpoint (RW)
0000
00C5 EP2_CR0: equ C5h ; EP2 Control Register 0 (#)
0080 EP2_CR0_STALL: equ 80h ; MASK: enable/disable stall (RW)
0020 EP2_CR0_NAK_INT_EN: equ 20h ; MASK: enable/disable NAK interrupts (RW)
0010 EP2_CR0_ACKD: equ 10h ; MASK: set when acked transaction occurs(RC)
000F EP2_CR0_MODE: equ 0Fh ; MASK: mode control for endpoint (RW)
0000
00C6 EP3_CR0: equ C6h ; EP3 Control Register 0 (#)
0080 EP3_CR0_STALL: equ 80h ; MASK: enable/disable stall (RW)
0020 EP3_CR0_NAK_INT_EN: equ 20h ; MASK: enable/disable NAK interrupts (RW)
0010 EP3_CR0_ACKD: equ 10h ; MASK: set when acked transaction occurs(RC)
000F EP3_CR0_MODE: equ 0Fh ; MASK: mode control for endpoint (RW)
0000
00C7 EP4_CR0: equ C7h ; EP4 Control Register 0 (#)
0080 EP4_CR0_STALL: equ 80h ; MASK: enable/disable stall (RW)
0020 EP4_CR0_NAK_INT_EN: equ 20h ; MASK: enable/disable NAK interrupts (RW)
0010 EP4_CR0_ACKD: equ 10h ; MASK: set when acked transaction occurs(RC)
000F EP4_CR0_MODE: equ 0Fh ; MASK: mode control for endpoint (RW)
0000
0000 ;------------------------------------------------
0000 ; Global Digital Interconnects
0000 ;------------------------------------------------
0000
00D0 GDI_O_IN: equ D0h ; Global Dig Interconnect Odd Inputs Reg (RW)
00D1 GDI_E_IN: equ D1h ; Global Dig Interconnect Even Inputs Reg (RW)
00D2 GDI_O_OU: equ D2h ; Global Dig Interconnect Odd Outputs Reg (RW)
00D3 GDI_E_OU: equ D3h ; Global Dig Interconnect Even Outputs Reg (RW)
0000
0000 ;------------------------------------------------
0000 ; AMuxBus Mux Control Registers
0000 ;------------------------------------------------
0000
00D8 MUX_CR0: equ D8h ; Analog Mux Bus Port 0 Bit Enables Reg (RW)
00D9 MUX_CR1: equ D9h ; Analog Mux Bus Port 1 Bit Enables Reg (RW)
00DA MUX_CR2: equ DAh ; Analog Mux Bus Port 2 Bit Enables Reg (RW)
00DB MUX_CR3: equ DBh ; Analog Mux Bus Port 3 Bit Enables Reg (RW)
00EC MUX_CR4: equ ECh ; Analog Mux Bus Port 4 Bit Enables Reg (RW)
00ED MUX_CR5: equ EDh ; Analog Mux Bus Port 5 Bit Enables Reg (RW)
0000
0000 ;------------------------------------------------
0000 ; Clock and System Control Registers
0000 ;------------------------------------------------
0000
00DD OSC_GO_EN: equ DDh ; Oscillator to Global Outputs Enable Register (RW)
0080 OSC_GOEN_SLPINT: equ 80h ; Enable Sleep Timer onto GOE[7]
0040 OSC_GOEN_VC3: equ 40h ; Enable VC3 onto GOE[6]
0020 OSC_GOEN_VC2: equ 20h ; Enable VC2 onto GOE[5]
0010 OSC_GOEN_VC1: equ 10h ; Enable VC1 onto GOE[4]
0008 OSC_GOEN_SYSCLKX2: equ 08h ; Enable 2X SysClk onto GOE[3]
0004 OSC_GOEN_SYSCLK: equ 04h ; Enable 1X SysClk onto GOE[2]
0002 OSC_GOEN_CLK24M: equ 02h ; Enable 24 MHz clock onto GOE[1]
0001 OSC_GOEN_CLK32K: equ 01h ; Enable 32 kHz clock onto GOE[0]
0000
00DE OSC_CR4: equ DEh ; Oscillator Control Register 4 (RW)
0003 OSC_CR4_VC3SEL: equ 03h ; MASK: System VC3 Clock source
0000
00DF OSC_CR3: equ DFh ; Oscillator Control Register 3 (RW)
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0004 VLT_CMP_PUMP: equ 04h ; MASK: Vcc below SMP trip level
0002 VLT_CMP_LVD: equ 02h ; MASK: Vcc below LVD trip level
0001 VLT_CMP_PPOR: equ 01h ; MASK: Vcc below PPOR trip level
0000
00E7 DEC_CR2: equ E7h ; Data Control Register 2 (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (RW)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (RW)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
00EF IMO_TR2: equ EFh ; Internal Main Oscillator Gain Trim Register (RW)
0000
00FD DAC_CR: equ FDh ; DAC Control Register (RW)
0080 DAC_CR_SPLIT_MUX: equ 80h ; MASK: enable/disable Splitting of AMuxBuses
0040 DAC_CR_MUXCLK_GE: equ 40h ; MASK: Connect/Disconnect AMuxBus to GOO[6]
0008 DAC_CR_RANGE: equ 08h ; MASK: High Range/Low Range
0006 DAC_CR_OSCMODE: equ 06h ; MASK: Sets Reset Mode for AMuxBus
0001 DAC_CR_ENABLE: equ 01h ; MASK: enable/disable AMux Bus
0000
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
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