?? board1.h
字號(hào):
/* - ERROR failure */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_sem_get(BrdSem sem);
/*****************************************************************************/
/* s16 brd_sem_wait(void) */
/* */
/* This routine tries to obtain the specified user semaphore. It blocks till*/
/* the semaphore is obtained. */
/* */
/* Parameters: */
/* - sem - desired semaphore */
/* */
/* Return: */
/* - OK success */
/* - ERROR failure */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_sem_wait(BrdSem sem);
/*****************************************************************************/
/* s16 brd_sem_release(void) */
/* */
/* This routine releases the previously obtained semaphore. */
/* */
/* Parameters: */
/* - sem - semaphore to release */
/* */
/* Return: */
/* - OK success */
/* - ERROR failure */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_sem_release(BrdSem sem);
/*****************************************************************************/
/* s16 brd_fifo_read (s8 *bufptr, u16 cnt) */
/* */
/* This routine begins a synchronous read from the fifo channel. */
/* */
/* Parameters: */
/* - p_buffer is the location of the data to be written to the FIFO */
/* - num_bytes is the number of bytes of data to be written to the FIFO, */
/* */
/* Return: */
/* - returns OK or ERROR, */
/* possible error conditions include: another send in progress, */
/* chan not open, no DMA chan available */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_fifo_read(char *bufptr, u16 cnt);
/*****************************************************************************/
/* s16 brd_fifo_write (s8 *bufptr, u16 cnt) */
/* */
/* This routine begins a synchronous read from the fifo channel. */
/* */
/* Parameters: */
/* - p_buffer is the location of the data to be written to the FIFO */
/* - num_bytes is the number of bytes of data to be written to the FIFO, */
/* */
/* Return: */
/* - returns OK or ERROR, */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_fifo_write(char *bufptr, u16 cnt);
/*****************************************************************************/
/* s16 brd_delay_msec(u16 msec) */
/* */
/* This routine delays execution by specified milliseconds. */
/* */
/* Parameters: */
/* - msec - time delay in milliseconds. */
/* */
/* Return: */
/* - TRUE success */
/* - FALSE failure */
/* */
/* Notes: */
/* */
/* The delay is implemented using timer 0 at port (0x24). Care must be */
/* taken not to interrupt timer operation by way of interrupts. */
/* Maximum supported delay is 6553 usec or 6.5 secs. */
/* */
/*****************************************************************************/
s16 brd_delay_msec(u16 msec);
/*****************************************************************************/
/* s16 brd_delay_usec(u16 usec) */
/* */
/* This routine delays execution by specified microseconds. */
/* */
/* Parameters: */
/* - usec - time delay in microseconds. */
/* */
/* Return: */
/* - TRUE success */
/* - FALSE failure */
/* */
/* Notes: */
/* */
/* The delay is implemented using timer 0 at port (0x24). Care must be */
/* taken not to interrupt timer operation by way of interrupts. */
/* Maximum supported delay is 65536 usec or 65.536 msecs. */
/* */
/*****************************************************************************/
s16 brd_delay_usec(u16 usec);
/*****************************************************************************/
/* s16 brd_set_wait_states(u16 flashDbProg, */
/* u16 data32_64, */
/* u16 io) */
/* */
/* This routine sets the wait states for program, data & I/O spaces */
/* */
/* Parameters: */
/* - extendedProg - dsk onboard external program memory wait states */
/* - flashDbProg - flash/daughter board memory wait states */
/* - data0_32 - first 32K data memory wait states */
/* - data32_64 - Second 32K data memory wait states */
/* - io - I/O wait states */
/* */
/* Return: */
/* - OK success */
/* - ERROR failure */
/* */
/* Notes: */
/* */
/*****************************************************************************/
s16 brd_set_wait_states(u16 flashDbProg,
u16 data32_64,
u16 io);
/*****************************************************************************/
/* brd_set_cpu_freq() */
/* */
/* This routine sets the CPU frequency */
/* */
/* Parameters: */
/* - freq frequency in MHz to set cpu clock */
/* */
/* Return: */
/* - void */
/* */
/* Notes: */
/* */
/* Board frequencies must be a multiple of 10 with the lowest being 20 MHz */
/* and the highest being 100 MHz. Board frequencies supported are: */
/* 20,30,40,50,60,70, */
/* */
/*****************************************************************************/
void brd_set_cpu_freq(u16 freq);
/*****************************************************************************/
/* brd_get_cpu_freq() */
/* */
/* This routine returns the CPU frequency */
/* */
/* Parameters: */
/* - None */
/* */
/* Return: */
/* - void */
/* */
/* Notes: */
/*****************************************************************************/
u16 brd_get_cpu_freq();
/*****************************************************************************/
/* brd_io_redir() */
/* */
/* This routine redirects printfs to the host terminal. */
/* */
/* Parameters: */
/* - None */
/* */
/* Return: */
/* - void */
/* */
/* Notes: */
/*****************************************************************************/
void brd_io_redir(bool enable);
/*****************************************************************************/
/* s16 brd_mem_transfer() */
/* */
/* This routine uses the DMA to transfer data from one mem location to the */
/* the other. */
/* */
/* Parameters: */
/* - ch : DMA channel to use. */
/* - src_addr - source address. */
/* - src_space - source memory space. Values in dma5410.h */
/* - dst_addr - destination address. */
/* - dst_space - destination memory space. Values in dma5410.h */
/* - cnt - number of words to transfer. */
/* - sync - wait for transfer to complete. */
/* Return: */
/* - OK success */
/* - ERROR failure */
/* */
/* Notes: */
/* - If channel is busy call waits for channel to be available. */
/* */
/*****************************************************************************/
s16 brd_mem_transfer(u16 ch, u16 *src_addr, u16 src_space,
u16 *dst_addr, u16 dst_space, u16 cnt, bool sync);
#endif /* end of #ifndef _BOARD_H */
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