#define DSYNC_REVT1           0x05     /* sync to McBSP1 receive event          */
#define AUTOINIT_ENABLE		0x01     /* auto-initialization mode is enabled   */
#define DINM_ENABLE		0x01     /* DMA interrupt is enabled              */
#define IMOD_HALFBLOCK        0x01     /* DMA Int occurs each half block        */
#define CTMOD_DEC			0x00     /* Decrement counter mode                */
#define INDEXMODE_NOMOD       0x00     /* No modify (Index mode)                */
#define INDEXMODE_INC	      0x01     /* Post increment index mode             */
#define HIGH_PRIORITY		0x01     /* Highest priority for DMA channel      */
#define INTSEL_01			0x01     /* RINT0,XINT0,RINT2,XINT2,DMAC2,DMAC3,  */
						   /* DMAC4,DMAC5                           */
#define DSYNC_XEVT1           0x06     /* sync to McBSP1 transmit event         */
#define IMOD_BLOCK		0x00     /* DMA Int occurs at the end of the block*/
#define CTMOD_DEC			0x00     /* Decrement counter mode                */
#define SPACE_DATA		0x01     /* DMA Data Space Select                 */

/* Memory-Mapped Register Definitions */
#define DMPREC               (*(volatile unsigned int*)(0x0054u))
#define DMSBA                (*(volatile unsigned int*)(0x0055u))
#define DMSDI                (*(volatile unsigned int*)(0x0056u))
#define DMSDN                (*(volatile unsigned int*)(0x0057u))

#define IMR	                 (*(volatile unsigned int*)(0x0000u))
#define IFR                  (*(volatile unsigned int*)(0x0001u))
#define XPC	                 (*(volatile unsigned int*)(0x001eu))
#define PMST	           (*(volatile unsigned int*)(0x001du))
#define BSCR                 (*(volatile unsigned int*)(0x0029u))




#define DRR1_ADDR(port)      (port ? 0x41 : 0x21)
#define DXR1_ADDR(port)      (port ? 0x43 : 0x23)

#define TCR_ADDR(port)       (port ? 0x32 : 0x26)
#define TCR(port)            (*(volatile unsigned int*)TCR_ADDR(port))

#define PRD_ADDR(port)       (port ? 0x31 : 0x25)
#define PRD(port)            (*(volatile unsigned int*)PRD_ADDR(port))

/* Sub Address Register Definitions */
#define DMSRC_SUBADDR	0x00
#define DMDST_SUBADDR	0x01
#define DMCTR_SUBADDR	0x02
#define DMSEFC_SUBADDR	0x03
#define DMMCR_SUBADDR	0x04

#define DMSRCP_SUBADDR	0x1E
#define DMDSTP_SUBADDR	0x1F
#define DMIDX0_SUBADDR	0x20
#define DMIDX1_SUBADDR	0x21
#define DMFRI0_SUBADDR	0x22
#define DMFRI1_SUBADDR	0x23           
#define DMGSA_SUBADDR	0x24
#define DMGDA_SUBADDR	0x25
#define DMGCR_SUBADDR	0x26
#define DMGFR_SUBADDR	0x27

/* Channel Definitions */
#define DMA_CH0         0
#define DMA_CH1         1
#define DMA_CH2         2
#define DMA_CH3         3
#define DMA_CH4         4
#define DMA_CH5         5

/* DMA Channel Flags for IMR/IFR */
#define DMAC0		6
#define DMAC1		7
#define DMAC2		10
#define DMAC3		11
#define DMAC4		12
#define DMAC5		13


/* Register Bit Fields */
#define TDDR		 0
#define TSS			 4                            
#define TRB          5

/* Macro Definitions */
/* DMA Framecount Set */
#define DMA_FRAMECOUNT(chan, value) \
        { DMSBA = (chan * 5) + DMSEFC_SUBADDR;\
          DMSDN = (DMSDN & 0xFF00u) | value;\
        }

/* DMA Channel Enable */
#define DMA_ENABLE(chan) \
          DMPREC |= (1 << chan);


#define INTR_GLOBAL_ENABLE\
        asm("\tRSBX	INTM")

#define INTR_CLR_FLAG(flag)\
      {IFR |= (0x1u << flag);}

#define INTR_ENABLE(flag)\
     {IMR |= ((0x1u) << flag);}

#define TIMER_HALT(port)\
        TCR(port) |= (0x1u << TSS)  
        
#define TIMER_START(port)\
        TCR(port) = (TCR(port) & (~(0x1u) << TSS)) | (0x1u << TRB)        

#define TIMER_RESET(port)\
	{ TIMER_HALT(port);\
          TCR(port) &= 0xFFF0u;\
          PRD(port) = 0xffffu;\
          TIMER_START(port); }

/* DMA Reset All */
static inline void dma_reset_all( void )
{
  unsigned short channel;

  DMPREC = 0x0000u;

  DMSBA  = DMSRC_SUBADDR;

  for (channel= 0;channel <= 4; channel++)
  {
      DMSDI = 0x0000u;             //src
      DMSDI = 0x0000u;             //dst
      DMSDI = 0x0000u;             //ctr
      DMSDI = 0x0000u;             //sefc
      DMSDI = 0x0000u;             //mcr
  }         
                                  

  DMSBA = DMSRCP_SUBADDR;

  DMSDI = 0x0000u;  /*DMSRCP*/
  DMSDI = 0x0000u;  /*DMDSTP*/
  
  DMSDI = 0x0000u;  /*DMIDX0*/
  DMSDI = 0x0000u;  /*DMIDX1*/
  DMSDI = 0x0000u;  /*DMFRI0*/
  DMSDI = 0x0000u;  /*DMFRI1*/          
  DMSDI = 0x0000u;  /*DMGSA*/
  DMSDI = 0x0000u;  /*DMGDA*/
  DMSDI = 0x0000u;  /*DMGCR*/
  DMSDI = 0x0000u;  /*DMGRF*/
}          

/* Initialize Global DMA Registers */
static inline void dma_global_init(
              unsigned int dmpre       /*IN:Value for priority and enable reg*/
             ,unsigned int dmsrcp      /*IN:Value for source page reg        */
             ,unsigned int dmdstp      /*IN:Value for dest page reg          */
             ,unsigned int dmidx0      /*IN:Value for element index reg 0    */
             ,unsigned int dmidx1      /*IN:Value for element index reg 1    */
             ,unsigned int dmfri0      /*IN:Value for frame index reg 0      */
             ,unsigned int dmfri1      /*IN:Value for frame index reg 1      */
             ,unsigned int dmgsa       /*IN:Value for global src addr reload */
             ,unsigned int dmgda       /*IN:Value for global dst addr reload */
             ,unsigned int dmgcr       /*IN:Value for global count reload reg*/
             ,unsigned int dmgfr)      /*IN:Value for global frame reload reg*/
{

  DMPREC &= 0xFF00u;       /* Temporarily Disable All Channels */
  DMSBA = DMSRCP_SUBADDR;  /* Set DMA SubBank Address Register */

  DMSDI = dmsrcp;    /* Write to DMA src subbank register with increment */
  DMSDI = dmdstp;
  DMSDI = dmidx0;
  DMSDI = dmidx1;
  DMSDI = dmfri0;
  DMSDI = dmfri1;
  DMSDI = dmgsa;
  DMSDI = dmgda;
  DMSDI = dmgcr;
  DMSDI = dmgfr;

  DMPREC = dmpre;
}

static inline void   dma_init(
             unsigned int channel      /*IN: DMA channel number              */
            ,unsigned int dmsefc       /*IN: Value to set sync & fr reg      */
            ,unsigned int dmmcr        /*IN: Value to set mode control reg   */
		,unsigned int dmctr	   /*IN: Value to set element count reg  */
            ,unsigned int src_page     /*IN: Value to set source page reg    */
            ,unsigned int src_addr     /*IN: Value to set source addr reg    */
            ,unsigned int dst_page     /*IN: Value to set dest page reg      */
            ,unsigned int dst_addr     /*IN: Value to set dest addr reg      */
                )
{
  DMSBA = (channel * 5) + DMSRC_SUBADDR;

  DMSDI = src_addr;     /* Write to DMA src subbank register with increment */
  DMSDI = dst_addr;
  DMSDI = dmctr;
  DMSDI = dmsefc;
  DMSDI = dmmcr;


  DMSBA = DMSRCP_SUBADDR;

  DMSDI = src_page;
  DMSDI = dst_page;  
}