=========Chip ver1=========Summary Information:--------------------Type: Initial implementationSource: out-of-dateStatus: 0 errors, 1 warnings, 6 messagesTarget Information:-------------------Vendor: XilinxFamily: SPARTANDevice: S10TQ144Speed: -4Chip Parameters:----------------Optimize for: SpeedOptimization effort: HighFrequency: 50 MHzIs module: NoKeep io pads: NoNumber of flip-flops: 0Number of latches: 0Chip Design Hierarchy:----------------------UART: defined in c:\phili\fndtn\miniuart\miniuart.vhd  Counter - Uart_Rxrate: defined in c:\phili\fndtn\miniuart\utils.vhd  Counter - Uart_Txrate: defined in c:\phili\fndtn\miniuart\utils.vhd  TxUnit - Uart_TxUnit: defined in c:\phili\fndtn\miniuart\txunit.vhd    synchroniser - SyncLoad: defined in c:\phili\fndtn\miniuart\utils.vhd  RxUnit - Uart_RxUnit: defined in c:\phili\fndtn\miniuart\rxunit.vhdPrimitive reference count:--------------------------*ADD_UNS_OP_2_1_2    1*ADD_UNS_OP_4_1_4    2*SELECT_OP_2.1_2.1_1    1*SELECT_OP_2.2_2.1_2    2*SELECT_OP_3.4_3.1_4    2*SUB_TC_OP_1_1_1    1*SUB_TC_OP_2_2_2    1*SUB_TC_OP_3_3_3    2AND         209SEQ          64Clocks:-------                           Required  Estimated                       Period   Rise     Fall     Freq      Freq       Signal               (ns)     (ns)     (ns)     (MHz)     (MHz)                           ............................................................... 20        0       10       50.00     -1.00     default               -1       -1       -1      -1000.00  100.00     BR_Clk_I              -1       -1       -1      -1000.00  100.00     LoadA                 -1       -1       -1      -1000.00  100.00     RRegL                 -1       -1       -1      -1000.00  100.00     WB_CLK_I             Timing Groups:--------------                                                                                                                                                          Name                           Description                                   ...........................................................................(I)                            Input ports                                   (O)                            Output ports                                  (RC,BR_Clk_I)                  Clocked by rising edge of BR_Clk_I            (RC,LoadA)                     Clocked by rising edge of LoadA               (RC,RRegL)                     Clocked by rising edge of RRegL               (RC,WB_CLK_I)                  Clocked by rising edge of WB_CLK_I            Timing Path Groups:-------------------                                                          Required  Estimated                                                           Delay     Delay     From                         To                           (ns)      (ns)      ..........................................................................(I)                          (O)                           20.00     -1.00    (I)                          (RC,BR_Clk_I)                 20.00     -1.00    (I)                          (RC,WB_CLK_I)                 20.00     -1.00    (RC,BR_Clk_I)                (O)                           20.00     -1.00    (RC,BR_Clk_I)                (RC,BR_Clk_I)                 20.00     -1.00    (RC,LoadA)                   (RC,BR_Clk_I)                 20.00     -1.00    (RC,RRegL)                   (O)                           20.00     -1.00    (RC,WB_CLK_I)                (RC,BR_Clk_I)                 20.00     -1.00    Input Port Timing:------------------                               Required   Estimated                            Port                           Delay      Slack                                Name                           (ns)       (ns)       To-Group                  ...........................................................................WB_CLK_I                        20.00      -1.00     (RC,BR_Clk_I)             WB_RST_I                        20.00      -1.00     (RC,BR_Clk_I)             WB_ADR_I<1>                     20.00      -1.00     (RC,BR_Clk_I)             WB_ADR_I<0>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<7>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<6>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<5>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<4>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<3>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<2>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<1>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_I<0>                     20.00      -1.00     (RC,BR_Clk_I)             WB_WE_I                         20.00      -1.00     (RC,BR_Clk_I)             WB_STB_I                        20.00      -1.00     (RC,BR_Clk_I)             BR_Clk_I                        20.00      -1.00     (RC,BR_Clk_I)             RxD_PAD_I                       20.00      -1.00     (RC,BR_Clk_I)             Output Port Timing:-------------------                               Required   Estimated                            Port                           Delay      Slack                                Name                           (ns)       (ns)       From-Group                ...........................................................................WB_DAT_O<7>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<6>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<5>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<4>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<3>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<2>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<1>                     20.00      -1.00     (RC,BR_Clk_I)             WB_DAT_O<0>                     20.00      -1.00     (RC,BR_Clk_I)             WB_ACK_O                        20.00      -1.00     (RC,BR_Clk_I)             IntTx_O                         20.00      -1.00     (RC,BR_Clk_I)             IntRx_O                         20.00      -1.00     (RC,BR_Clk_I)             TxD_PAD_O                       20.00      -1.00     (RC,BR_Clk_I)