onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/cntrl/instruction_reg
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/exc_en_o
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/core/cntrl/pc_reg
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu1/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu1/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/o2data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu1/o2load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu1/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu2/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu2/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/o2data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu2/o2load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu2/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu3/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu3/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/o2data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu3/o2load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu3/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu4/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu4/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/o2data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu4/o2load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu4/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu23/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu23/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu23/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu23/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu23/o1load
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu23/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu21/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu21/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu21/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu21/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu21/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu21/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu21/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu22/t1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu22/t1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu22/t1opcode
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu22/o1data
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/core/fu22/o1load
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu22/r1data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/fu22/r2data
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_q_0
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_d_0
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_addr_0
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/dmem_en_x_0
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/dmem_wr_x_0
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_bit_wr_x_0
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_q_1
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_d_1
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_addr_1
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/dmem_en_x_1
add wave -noupdate -format Logic -radix hexadecimal /testbench/chip/move/dmem_wr_x_1
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/dmem_bit_wr_x_1
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/rf1/regfile
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/rf2/regfile
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/rf3/regfile
add wave -noupdate -format Literal -radix hexadecimal /testbench/chip/move/core/rf4/regfile
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/reqCnt
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/hitRCnt
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/hitWCnt
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/missRCnt
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/missWCnt
add wave -noupdate -format Literal -radix decimal /testbench/chip/move/dcache/DcacheL1/missPCnt
add wave -noupdate -format Logic /testbench/chip/move/core/clk
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {77986 ns} 0}
configure wave -namecolwidth 278
configure wave -valuecolwidth 96
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ns} {105344 ns}