?? ccreg.h
字號:
#ifndef CCREG_H
#define CCREG_H
#define RFMAXLENGTH 30
// CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER
#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
#define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
#define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
#define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
#define CCxxx0_SYNC1 0x04 // Sync word, high byte
#define CCxxx0_SYNC0 0x05 // Sync word, low byte
#define CCxxx0_PKTLEN 0x06 // Packet length
#define CCxxx0_PKTCTRL1 0x07 // Packet automation control
#define CCxxx0_PKTCTRL0 0x08 // Packet automation control
#define CCxxx0_ADDR 0x09 // Device address
#define CCxxx0_CHANNR 0x0A // Channel number
#define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
#define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
#define CCxxx0_FREQ2 0x0D // Frequency control word, high byte
#define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte
#define CCxxx0_FREQ0 0x0F // Frequency control word, low byte
#define CCxxx0_MDMCFG4 0x10 // Modem configuration
#define CCxxx0_MDMCFG3 0x11 // Modem configuration
#define CCxxx0_MDMCFG2 0x12 // Modem configuration
#define CCxxx0_MDMCFG1 0x13 // Modem configuration
#define CCxxx0_MDMCFG0 0x14 // Modem configuration
#define CCxxx0_DEVIATN 0x15 // Modem deviation setting
#define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
#define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
#define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
#define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
#define CCxxx0_AGCCTRL2 0x1B // AGC control
#define CCxxx0_AGCCTRL1 0x1C // AGC control
#define CCxxx0_AGCCTRL0 0x1D // AGC control
#define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout
#define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout
#define CCxxx0_WORCTRL 0x20 // Wake On Radio control
#define CCxxx0_FREND1 0x21 // Front end RX configuration
#define CCxxx0_FREND0 0x22 // Front end TX configuration
#define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
#define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
#define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
#define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
#define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
#define CCxxx0_PTEST 0x2A // Production test
#define CCxxx0_AGCTEST 0x2B // AGC test
#define CCxxx0_TEST2 0x2C // Various test settings
#define CCxxx0_TEST1 0x2D // Various test settings
#define CCxxx0_TEST0 0x2E // Various test settings
// Command strobes
#define CCxxx0_SRES 0x30 // Reset chip.
#define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
// If in RX/TX: Go to a wait state where only the synthesizer is
// running (for quick RX / TX turnaround).
#define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
#define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
// (enables quick start).
#define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
// MCSM0.FS_AUTOCAL=1.
#define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
// MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
// Only go to TX if channel is clear.
#define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
// Wake-On-Radio mode if applicable.
#define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
#define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
#define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
#define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
#define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
#define CCxxx0_SWORRST 0x3C // Reset real time clock.
#define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
// bytes for simpler software.
// Status registers
#define CCxxx0_PARTNUM 0x30
#define CCxxx0_VERSION 0x31
#define CCxxx0_FREQEST 0x32
#define CCxxx0_LQI 0x33 // CRC_Ok | LOI_EST[6.0]
#define CCxxx0_RSSI 0x34
#define CCxxx0_MARCSTATE 0x35 // REV | MARC_STATE[4.0]
#define CCxxx0_WORTIME1 0x36
#define CCxxx0_WORTIME0 0x37
#define CCxxx0_PKTSTATUS 0x38 // CRC_OK | CS | PQT_PEACHED | CCA | SFD | GDO2 | GDO1 | GDO0
#define CCxxx0_VCO_VC_DAC 0x39
#define CCxxx0_TXBYTES 0x3A // RXFIFO_UNDERFLOW | NUM_TXBYTES[6.0]
#define CCxxx0_RXBYTES 0x3B // RXFIFO_OVERFLOW | NUM_RXBYTES[6.0]
#define CCxxx0_PATABLE 0x3E
#define CCxxx0_TXFIFO 0x3F
#define CCxxx0_RXFIFO 0x3F
// GDOX_CFG
#define GDO_RXFIFO_FULL0 0x00
#define GDO_RXFIFO_FULL 0x01
#define GDO_TXFIFO_FULL0 0x02
#define GDO_TXFIFO_FULL 0x03
#define GDO_RXFIFO_OVER 0x04
#define GDO_TXFIFO_UNDER 0x05
#define GDO_SYNC_END 0x06
#define GDO_NEW_PKT 0x07
#define GDO_PQI 0x08
#define GDO_CCA 0x09
#define GDO_LOCK_DETECTOR 0x0A
#define GDO_SERIAL_CLK 0x0B
#define GDO_SERIAL_DO_SY 0x0C
#define GDO_SERIAL_DO_AS 0x0D
#define GDO_CARRY_SENSE 0x0E
#define GDO_CRC_OK 0x0F
#define GDO_RX_HARD_DATA1 0x16
#define GDO_RX_HARD_DATA0 0x17
#define GDO_PA_PD 0x1B
#define GDO_LNA_PD 0x1C
#define GDO_RX_SYMBOL_TICK 0x1D
#define GDO_CHIP_RDY 0x29
#define GDO_XOSC_STABLE 0x2B
#define GDO_GDO0_DI 0x2D
#define GDO_HIGH_IMPEDANCE 0x2E
#define GDO_HW_0 0x2F
#define GDO_XOSC_1 0x30
#define GDO_XOSC_1_5 0x31
#define GDO_XOSC_2 0x32
#define GDO_XOSC_3 0x33
#define GDO_XOSC_4 0x34
#define GDO_XOSC_6 0x35
#define GDO_XOSC_8 0x36
#define GDO_XOSC_12 0x37
#define GDO_XOSC_16 0x38
#define GDO_XOSC_24 0x39
#define GDO_XOSC_32 0x3A
#define GDO_XOSC_48 0x3B
#define GDO_XOSC_64 0x3C
#define GDO_XOSC_96 0x3D
#define GDO_XOSC_128 0x3E
#define GDO_XOSC_192 0x3F
// STATUS BYTE
//CHIP_RDY | STATE[2.0] | FIFO_BYTES_AVALIABLE[3.0]
#define CCST_IDLE 0x00
#define CCST_RX 0x01
#define CCST_TX 0x02
#define CCST_FSTXON 0x03
#define CCST_CALIBRATE 0x04
#define CCST_SETTING 0x05
#define CCST_RXFIFO_OVER 0x06
#define CCST_TXFIFO_UNDER 0x07
// Read/Write mask
#define WRITE_BURST 0x40
#define READ_SINGLE 0x80
#define READ_BURST 0xC0
#define CRC_OK 0x80
#define RSSI 0
#define LQI 1
#define BYTES_IN_RXFIFO 0x7F
// RFxCTRL
#define RF_SLEEP B0000_0000 //0x00
#define RF_SEND B0000_0001 //0x01
#define RF_RECEIVE B0000_0010 //0x02
#define RF_SEND_OVER B0000_0101 //0x05
#define RF_RECEIVE_OVER B0000_0110 //0x06
#define RF_SEND_ERR B0000_1001 //0x09
#define RF_RECEIVE_ERR B0000_1010 //0x0a
#define RF_INTERR B0001_0000 //0x10
#define RF_TIMERR B0010_0000 //0x20
#define RF_EVENT_MIN 0x03
#define RF_BUSY_MASK 0x03
#define RF_USE_FIXBUF
#define RF_USE_CCA
#define RF_USE_SCAL
#define RSSI_OFFSET 76
#ifdef RF_USE_FIXBUF
#define RFTXBUF RfTxBuf
#define RFRXBUF RfRxBuf
#endif
#define RF_TX_TIME 2
#define RF_MASTER_TIME 3
//#define RF_WAITER_TIME 12
#define RFBUFSIZE 25
#define RLENGTH_MAX RFBUFSIZE-1
//---------------------------Package Format-------------------------------------------------//
// |<----------Optional data whitening------------------>| //
// |<-------Optionally FEC encoded/decoded-------------->| //
// |<-------Optional CRC_16 calculation-------->| //
// |<-Inserted automatically-->|<---------Optional--------->|<-Unprocessed->|<-Auto->| //
// |Preamble bits | Sync word |Length field |Address field | Data field | CRC_16 | //
// | 8*n bits | 16/32 bits| 8 bits | 8 bits | 8*n bits | 16 bits| //
//------------------------------------------------------------------------------------------//
//38.4kbps 4.8Kbytes
//
#endif
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -