-- Implementation of a free running fixed frequency oscillator using a DCM.
-- Frequency generated will be approximately 145MHz in a Spartan-3E device.
--
-- Important note - This design is for evaluation purposes only.
--                  Only contact the author directly if you have any questions about your 
--                  evaluation of this DCM test mode. 
--
-- Version : 1.12
-- Date : 28th February 2006
--
-- Ken Chapman
-- Xilinx Ltd
--
-- chapman@xilinx.com
--
--
------------------------------------------------------------------------------------
--
-- HOW TO USE
--
------------------------------------------------------------------------------------
--
--
-- This design is for SPARTAN-3E devices only.
--
-- Special set up required to process this design with ISE tools.
--
-- 1) Set an environment variable called XIL_TEST_ARCS
--    My_computer -> properties -> advanced -> Environment variables
--        System variables -> New -> 
--            XIL_TEST_ARCS with value = 1
--    Make sure the Xilinx tools are closed and opened again before using.
--
-- 2) Compile the design and download to the device.
--       'dcm_spar3_test' will appear to be an unrecognised entity but this can be ignored.
--       Warnings concerning unexpected feedback loops and DCM timing can also be ignored.
--  
-- 3) Apply any signal to 'kick start' so that it is waggled a few times.
--    The oscillator will then burst into life at approximately 145MHz.
--    The output frequency is not related to the kick start signal in any way.
--
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2006.   This code may be contain portions patented by other 
-- third parties.  By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard 
-- is free from any claims of infringement by any third party.  Xilinx expressly 
-- disclaims any warranty with respect to the adequacy of the implementation, including 
-- but not limited to any warranty or representation that the implementation is free 
-- from claims of any third party.  Furthermore, Xilinx is providing this core as a 
-- courtesy to you and suggests that you contact all third parties to obtain the 
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
--
-- Library declarations
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
-- Main Entity for dcm_fixed_osc
--
entity dcm_fixed_osc is
  port(    clk_out : out std_logic;
        kick_start : in std_logic   );
  end dcm_fixed_osc;


--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for dcm_fixed_osc
--	 
architecture low_level_definition of dcm_fixed_osc is
--
------------------------------------------------------------------------------------
--
-- Definition of the special DCM test primitive
--
------------------------------------------------------------------------------------
--

component DCM_SPAR3_TEST
  generic
      (CLKIN_PERIOD : real := 20.0);   -- Avoids a MAP warning but actual value not so important.
  port(	  CLKIN : in std_ulogic;
            CTLMODE : in std_ulogic;
              CLKFX : out std_ulogic);
   end component;  

--
------------------------------------------------------------------------------------
--	
-- Circuit description
--
------------------------------------------------------------------------------------
--	
begin

  fixed_osc_dcm: DCM_SPAR3_TEST
  port map (   CLKIN => kick_start,        
             CTLMODE => '1',            
               CLKFX => clk_out);

end low_level_definition;

------------------------------------------------------------------------------------
--
-- END OF FILE dcm_fixed_osc.VHD
--
------------------------------------------------------------------------------------