?? noise.rtw
字號:
Width 1
Dimensions [1, 1]
Tunable on
StorageClass Auto
NeedParenthesis 1
StringTransformed ""
Value [0.0]
}
DataInputPortDefaults {
RecordType DataInputPort
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
SystemToCall [-1, -1]
ComplexSignal no
FrameData no
RecurseOnInput 0
HaveGround no
BufferDstPort -1
AllowScalarExpandedExpr 0
}
HiddenDataInputPortDefaults {
RecordType DataInputPort
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
SystemToCall [-1, -1]
ComplexSignal no
FrameData no
RecurseOnInput 0
HaveGround no
BufferDstPort -1
AllowScalarExpandedExpr 0
}
ControlInputPortDefaults {
RecordType ControlInputPort
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
FrameData no
RecurseOnInput 0
HaveGround no
BufferDstPort -1
}
HiddenControlInputPortDefaults {
RecordType ControlInputPort
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
FrameData no
RecurseOnInput 0
HaveGround no
BufferDstPort -1
}
DataOutputPortDefaults {
RecordType DataOutputPort
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
OutputExpression 0
TrivialOutputExpression 0
FrameData no
Dimensions [-1,-1]
}
CanonicalInputArgDefaults {
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
}
CanonicalInputArgDefDefaults {
Identifier ""
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
StorageClass Auto
}
CanonicalOutputArgDefaults {
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
}
CanonicalOutputArgDefDefaults {
Identifier ""
SignalSrc []
SignalOffset [0]
Width 1
DataTypeIdx 0
ComplexSignal no
StorageClass Auto
}
CanonicalDWorkArgDefaults {
SignalSrc []
}
CanonicalDWorkArgDefDefaults {
FirstSignalSrc []
}
ModelParameters {
NumParameters 29
NumInrtP 29
NumConstPrms 0
NumExportedGlobal 0
NumImportedExtern 0
NumImportedExternPointer 0
NumCustomStorageClass 0
ParameterDefaults {
RecordType ModelParameter
MemoryMapIdx [-1,-1,-1]
HasObject 0
DataTypeIdx 0
OriginalDataTypeIdx 0
ComplexSignal 0
Width 1
Dimensions [1, 1]
Tunable yes
RollVarDeclared 0
Transformed no
StorageClass Auto
CustomStorageClassVersion 0
TypeQualifier ""
IsSfcnSizePrm 0
SystemScoping [0, 0]
Value [0.0]
AcceleratorPadding 0
}
Parameter {
Identifier Sine_Wave2_Amp
LogicalSrc P0
SystemScoping [0, 1]
ReferencedBy Matrix(1,4)
[[0, -1, 0, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave2_Bias
LogicalSrc P1
ReferencedBy Matrix(1,4)
[[0, -1, 0, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave2_Freq
LogicalSrc P2
Value [20000.0]
ReferencedBy Matrix(1,4)
[[0, -1, 0, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave2_Phase
LogicalSrc P3
ReferencedBy Matrix(1,4)
[[0, -1, 0, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Kp3_Gain
LogicalSrc P4
ReferencedBy Matrix(1,4)
[[0, -1, 1, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave4_Amp
LogicalSrc P5
Value [10.0]
ReferencedBy Matrix(1,4)
[[0, -1, 3, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave4_Bias
LogicalSrc P6
ReferencedBy Matrix(1,4)
[[0, -1, 3, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave4_Freq
LogicalSrc P7
Value [70.0]
ReferencedBy Matrix(1,4)
[[0, -1, 3, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave4_Phase
LogicalSrc P8
ReferencedBy Matrix(1,4)
[[0, -1, 3, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave3_Amp
LogicalSrc P9
Value [10.0]
ReferencedBy Matrix(1,4)
[[0, -1, 4, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave3_Bias
LogicalSrc P10
ReferencedBy Matrix(1,4)
[[0, -1, 4, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave3_Freq
LogicalSrc P11
Value [200.0]
ReferencedBy Matrix(1,4)
[[0, -1, 4, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave3_Phase
LogicalSrc P12
Value [1.0]
ReferencedBy Matrix(1,4)
[[0, -1, 4, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave_Amp
LogicalSrc P13
Value [10.0]
ReferencedBy Matrix(1,4)
[[0, -1, 5, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave_Bias
LogicalSrc P14
ReferencedBy Matrix(1,4)
[[0, -1, 5, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave_Freq
LogicalSrc P15
Value [500.0]
ReferencedBy Matrix(1,4)
[[0, -1, 5, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave_Phase
LogicalSrc P16
Value [2.0]
ReferencedBy Matrix(1,4)
[[0, -1, 5, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave1_Amp
LogicalSrc P17
Value [10.0]
ReferencedBy Matrix(1,4)
[[0, -1, 6, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave1_Bias
LogicalSrc P18
ReferencedBy Matrix(1,4)
[[0, -1, 6, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave1_Freq
LogicalSrc P19
Value [800.0]
ReferencedBy Matrix(1,4)
[[0, -1, 6, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave1_Phase
LogicalSrc P20
Value [3.0]
ReferencedBy Matrix(1,4)
[[0, -1, 6, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave5_Amp
LogicalSrc P21
Value [10.0]
ReferencedBy Matrix(1,4)
[[0, -1, 7, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave5_Bias
LogicalSrc P22
ReferencedBy Matrix(1,4)
[[0, -1, 7, 1];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave5_Freq
LogicalSrc P23
Value [1200.0]
ReferencedBy Matrix(1,4)
[[0, -1, 7, 2];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Sine_Wave5_Phase
LogicalSrc P24
Value [3.0]
ReferencedBy Matrix(1,4)
[[0, -1, 7, 3];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Kp2_Gain
LogicalSrc P25
Value [1.0]
ReferencedBy Matrix(1,4)
[[0, -1, 10, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier step_Value
LogicalSrc P26
Value [1.0000000000000001e-005]
ReferencedBy Matrix(1,4)
[[0, -1, 13, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Unit_Delay_X0
LogicalSrc P27
ReferencedBy Matrix(1,4)
[[0, -1, 14, 0];]
OwnerSysIdx [0, -1]
}
Parameter {
Identifier Kp4_Gain
LogicalSrc P28
Value [0.20000000000000001]
ReferencedBy Matrix(1,4)
[[0, -1, 17, 0];]
OwnerSysIdx [0, -1]
}
}
ReducedBlocks {
NumReducedBlocks 0
}
CustomStorageClasses {
NumCustomStorageClasses 0
}
SignalDefaults {
SigLabel ""
OutputPort [0, 1]
SignalOffset [0]
}
RootSignals {
ChildSubsystemIndices []
NumSignals 18
Signal {
Block [0, -1, 23]
SignalSrc [B9]
}
Signal {
Block [0, -1, 10]
SignalSrc [B3]
}
Signal {
Block [0, -1, 1]
SignalSrc [B0]
}
Signal {
Block [0, -1, 17]
SignalSrc [L0]
}
Signal {
Block "<Root>/Mux"
OutputPort [0, 3]
SignalSrc [B4, C0, B5]
SignalOffset [0, 0, 0]
}
Signal {
Block [0, -1, 16]
SignalSrc [B7]
}
Signal {
Block [0, -1, 9]
SignalSrc [B2]
}
Signal {
Block [0, -1, 5]
SignalSrc [L2]
}
Signal {
Block [0, -1, 6]
SignalSrc [L3]
}
Signal {
Block [0, -1, 0]
SignalSrc [L5]
}
Signal {
Block [0, -1, 4]
SignalSrc [L1]
}
Signal {
Block [0, -1, 3]
SignalSrc [L5]
}
Signal {
Block [0, -1, 7]
SignalSrc [L4]
}
Signal {
Block [0, -1, 8]
SignalSrc [B1]
}
Signal {
Block [0, -1, 18]
SignalSrc [B8]
}
Signal {
Block [0, -1, 12]
SignalSrc [B4]
}
Signal {
Block [0, -1, 14]
SignalSrc [B5]
}
Signal {
Block [0, -1, 13]
SignalSrc [C0]
}
NumBlocks 24
BlockSysIdx [0@24]
BlockMap [0:14, 16:24]
}
NumSubsystems 0
CanonicalPrmArgDefDefaults {
Dimensions [1, 1]
OriginalDataTypeIdx 0
DataTypeIdx 0
ComplexSignal no
}
NumSystems 1
System {
Type root
Name "<Root>"
Identifier noise
RTWSystemCode 2
ForceNonInline 0
SystemIdx 0
SL_SystemIdx 0
HStructDeclSystemIdx 0
NumHStructChildSystems 0
NumChildSystems 0
Interface {
NumCanonicalInputArgDefs 0
BlockIOArgDef {
FirstLocation 0
NumFlatFields 10
}
ConstBlockIOArgDef {
FirstLocation 0
NumFlatFields 0
}
NumCanonicalOutputArgDefs 0
PrmArgDef {
FirstLocation 0
NumFlatFields 29
PassthroughSystemIdx -1
}
NumCanonicalPrmArgDefs 0
DWorkArgDef {
FirstLocation 0
NumFlatFields 8
}
ContStatesArgDef {
FirstLocation 0
NumFlatFields 0
}
ContStatesDerivativeArgDef {
}
ContStatesDisabledArgDef {
}
NonsampledZCArgDef {
FirstLocation 0
NumFlatFields 0
}
ZCEventArgDef {
FirstLocation 0
NumFlatFields 0
}
RTMArgDef {
}
NumCanonicalDWorkArgDefs 0
}
Variables {
LocalBlockIODef {
FirstLocation 0
NumFlatFields 6
}
ExternBlockIODef {
FirstLocation 0
NumFlatFields 0
}
}
RunFcnCallSSInMinorStep no
TriggerBlkIdx -1
TriggerBlkReset 0
StatesCanReset no
NumZCEvents 0
FileNameOwnerIdx 0
IncludedChildSystemIdx []
NumBlocks 25
NumVirtualOutportBlocks 0
VirtualOutportBlocksIdx 25
NumTotalBlocks 25
Block {
Type Sin
BlockIdx [0, 0, 0]
ExprCommentInfo {
SysIdxList []
BlkIdxList []
}
ExprCommentSrcIdx {
SysIdx -1
BlkIdx -1
}
Name "<Root>/Sine Wave2"
Identifier Sine_Wave2
TID 0
RollRegions [0]
NumDataOutputPorts 1
DataOutputPort {
SignalSrc [L5]
}
ParamSettings {
SineType "Time based"
}
Parameters [4, 4]
Parameter {
Name "Amplitude"
ASTNode {
IsNonTerminal 0
Op SL_NOT_INLINED
ModelParameterIdx 0
}
String "0"
StringType "Expression"
NeedParenthesis 0
}
Parameter {
Name "Bias"
ASTNode {
IsNonTerminal 0
Op SL_NOT_INLINED
ModelParameterIdx 1
}
String "0"
StringType "Expression"
NeedParenthesis 0
}
Parameter {
Name "Frequency"
ASTNode {
IsNonTerminal 0
Op SL_NOT_INLINED
ModelParameterIdx 2
}
Value [20000.0]
String "20000"
StringType "Expression"
NeedParenthesis 0
}
Parameter {
Name "Phase"
ASTNode {
IsNonTerminal 0
Op SL_NOT_INLINED
ModelParameterIdx 3
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