/* system.h * * Machine generated for a CPU named "cpu_0" as defined in: * E:\DE2\DE2_demonstrations\DE2_SD_Card_Audio\nios_0.ptf * * Generated: 2007-04-13 22:06:50.937 * */#ifndef __SYSTEM_H_#define __SYSTEM_H_/*DO NOT MODIFY THIS FILE   Changing this file will have subtle consequences   which will almost certainly lead to a nonfunctioning   system. If you do modify this file, be aware that your   changes will be overwritten and lost when this file   is generated again.DO NOT MODIFY THIS FILE*//*******************************************************************************                                                                             ** License Agreement                                                           **                                                                             ** Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           ** All rights reserved.                                                        **                                                                             ** Permission is hereby granted, free of charge, to any person obtaining a     ** copy of this software and associated documentation files (the "Software"),  ** to deal in the Software without restriction, including without limitation   ** the rights to use, copy, modify, merge, publish, distribute, sublicense,    ** and/or sell copies of the Software, and to permit persons to whom the       ** Software is furnished to do so, subject to the following conditions:        **                                                                             ** The above copyright notice and this permission notice shall be included in  ** all copies or substantial portions of the Software.                         **                                                                             ** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  ** IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    ** FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ** AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      ** LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     ** FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         ** DEALINGS IN THE SOFTWARE.                                                   **                                                                             ** This agreement shall be governed in all respects by the laws of the State   ** of California and by the laws of the United States of America.              **                                                                             *******************************************************************************//* * system configuration * */#define ALT_SYSTEM_NAME "nios_0"#define ALT_CPU_NAME "cpu_0"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "CYCLONE"#define UP4#define ALT_STDIN "/dev/jtag_uart_0"#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"#define ALT_STDIN_BASE 0x01004000#define ALT_STDOUT "/dev/jtag_uart_0"#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"#define ALT_STDOUT_BASE 0x01004000#define ALT_STDERR "/dev/jtag_uart_0"#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"#define ALT_STDERR_BASE 0x01004000#define ALT_CPU_FREQ 50000000#define ALT_IRQ_BASE NULL/* * processor configuration * */#define NIOS2_CPU_IMPLEMENTATION "fast"#define NIOS2_BIG_ENDIAN 0#define NIOS2_ICACHE_SIZE 4096#define NIOS2_DCACHE_SIZE 2048#define NIOS2_ICACHE_LINE_SIZE 32#define NIOS2_ICACHE_LINE_SIZE_LOG2 5#define NIOS2_DCACHE_LINE_SIZE 4#define NIOS2_DCACHE_LINE_SIZE_LOG2 2#define NIOS2_FLUSHDA_SUPPORTED#define NIOS2_EXCEPTION_ADDR 0x00000020#define NIOS2_RESET_ADDR 0x00900800#define NIOS2_BREAK_ADDR 0x01000020#define NIOS2_HAS_DEBUG_STUB#define NIOS2_CPU_ID_SIZE 1#define NIOS2_CPU_ID_VALUE 0/* * A define for each class of peripheral * */#define __ALTERA_AVALON_JTAG_UART#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER#define __ALTERA_AVALON_TRI_STATE_BRIDGE#define __ALTERA_AVALON_CFI_FLASH#define __ALTERA_AVALON_TIMER#define __ALTERA_AVALON_SYSID#define __ALTERA_AVALON_UART#define __ALTERA_AVALON_LCD_16207#define __ALTERA_AVALON_PIO#define __USER_LOGIC_SEG7_LUT_8#define __USER_LOGIC_SRAM_16BITS_512K#define __USER_LOGIC_OPEN_I2C#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER#define __ALTERA_AVALON_USER_DEFINED_INTERFACE#define __USER_LOGIC_DM9000A/* * jtag_uart_0 configuration * */#define JTAG_UART_0_NAME "/dev/jtag_uart_0"#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"#define JTAG_UART_0_BASE 0x01004000#define JTAG_UART_0_SPAN 8#define JTAG_UART_0_IRQ 1#define JTAG_UART_0_WRITE_DEPTH 64#define JTAG_UART_0_READ_DEPTH 64#define JTAG_UART_0_WRITE_THRESHOLD 8#define JTAG_UART_0_READ_THRESHOLD 8#define JTAG_UART_0_READ_CHAR_STREAM ""#define JTAG_UART_0_SHOWASCII 1#define JTAG_UART_0_READ_LE 0#define JTAG_UART_0_WRITE_LE 0#define JTAG_UART_0_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0/* * sdram_0 configuration * */#define SDRAM_0_NAME "/dev/sdram_0"#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"#define SDRAM_0_BASE 0x00000000#define SDRAM_0_SPAN 8388608#define SDRAM_0_REGISTER_DATA_IN 1#define SDRAM_0_SIM_MODEL_BASE 1#define SDRAM_0_SDRAM_DATA_WIDTH 16#define SDRAM_0_SDRAM_ADDR_WIDTH 12#define SDRAM_0_SDRAM_ROW_WIDTH 12#define SDRAM_0_SDRAM_COL_WIDTH 8#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1#define SDRAM_0_SDRAM_NUM_BANKS 4#define SDRAM_0_REFRESH_PERIOD 15.625#define SDRAM_0_POWERUP_DELAY 100#define SDRAM_0_CAS_LATENCY 3#define SDRAM_0_T_RFC 70#define SDRAM_0_T_RP 20#define SDRAM_0_T_MRD 3#define SDRAM_0_T_RCD 20#define SDRAM_0_T_AC 5.5#define SDRAM_0_T_WR 14#define SDRAM_0_INIT_REFRESH_COMMANDS 2#define SDRAM_0_INIT_NOP_DELAY 0#define SDRAM_0_SHARED_DATA 0#define SDRAM_0_STARVATION_INDICATOR 0#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""#define SDRAM_0_IS_INITIALIZED 1#define SDRAM_0_SDRAM_BANK_WIDTH 2/* * tri_state_bridge_0 configuration * */#define TRI_STATE_BRIDGE_0_NAME "/dev/tri_state_bridge_0"#define TRI_STATE_BRIDGE_0_TYPE "altera_avalon_tri_state_bridge"/* * cfi_flash_0 configuration * */#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"#define CFI_FLASH_0_TYPE "altera_avalon_cfi_flash"#define CFI_FLASH_0_BASE 0x00800000#define CFI_FLASH_0_SPAN 1048576#define CFI_FLASH_0_SETUP_VALUE 40#define CFI_FLASH_0_WAIT_VALUE 160#define CFI_FLASH_0_HOLD_VALUE 40#define CFI_FLASH_0_TIMING_UNITS "ns"#define CFI_FLASH_0_UNIT_MULTIPLIER 1#define CFI_FLASH_0_SIZE 1048576/* * timer_0 configuration * */#define TIMER_0_NAME "/dev/timer_0"#define TIMER_0_TYPE "altera_avalon_timer"#define TIMER_0_BASE 0x00900000#define TIMER_0_SPAN 32#define TIMER_0_IRQ 0#define TIMER_0_ALWAYS_RUN 0#define TIMER_0_FIXED_PERIOD 0#define TIMER_0_SNAPSHOT 1#define TIMER_0_PERIOD 1#define TIMER_0_PERIOD_UNITS "ms"#define TIMER_0_RESET_OUTPUT 0#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0#define TIMER_0_MULT 0.001#define TIMER_0_FREQ 50000000/* * sysid configuration * */#define SYSID_NAME "/dev/sysid"#define SYSID_TYPE "altera_avalon_sysid"#define SYSID_BASE 0x00900020#define SYSID_SPAN 8#define SYSID_ID 3956160735u#define SYSID_TIMESTAMP 1126699666u/* * uart_0 configuration * */#define UART_0_NAME "/dev/uart_0"#define UART_0_TYPE "altera_avalon_uart"#define UART_0_BASE 0x00900040#define UART_0_SPAN 32#define UART_0_IRQ 2#define UART_0_BAUD 115200#define UART_0_DATA_BITS 8#define UART_0_FIXED_BAUD 1#define UART_0_PARITY 'N'#define UART_0_STOP_BITS 1#define UART_0_USE_CTS_RTS 0#define UART_0_USE_EOP_REGISTER 0#define UART_0_SIM_TRUE_BAUD 0#define UART_0_SIM_CHAR_STREAM ""#define UART_0_FREQ 50000000/* * timer_1 configuration * */#define TIMER_1_NAME "/dev/timer_1"#define TIMER_1_TYPE "altera_avalon_timer"#define TIMER_1_BASE 0x00900060#define TIMER_1_SPAN 32#define TIMER_1_IRQ 3#define TIMER_1_ALWAYS_RUN 0#define TIMER_1_FIXED_PERIOD 0#define TIMER_1_SNAPSHOT 1#define TIMER_1_PERIOD 1#define TIMER_1_PERIOD_UNITS "ms"#define TIMER_1_RESET_OUTPUT 0#define TIMER_1_TIMEOUT_PULSE_OUTPUT 0#define TIMER_1_MULT 0.001#define TIMER_1_FREQ 50000000/* * lcd_16207_0 configuration * */#define LCD_16207_0_NAME "/dev/lcd_16207_0"#define LCD_16207_0_TYPE "altera_avalon_lcd_16207"#define LCD_16207_0_BASE 0x00900030#define LCD_16207_0_SPAN 16/* * led_green configuration * */#define LED_GREEN_NAME "/dev/led_green"#define LED_GREEN_TYPE "altera_avalon_pio"#define LED_GREEN_BASE 0x009000C0#define LED_GREEN_SPAN 16#define LED_GREEN_DO_TEST_BENCH_WIRING 0