?? pnl_chilin084_at.h
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#include "ms_reg.h"
#ifndef _PNL_PVI07_H_
#define _PNL_PVI07_H_
#include "devvd.h"
#define PanelName "PnlChiLin084"
#define WidePanel 1
#define PANEL_DOT_WIDTH 107 // unit: um
#define PANEL_DOT_HEIGHT 370 // unit: um
#define PanelDither 8
#define PANEL_TTL 0
#define PANEL_DIGITAL_TCON 0
#define PANEL_ANALOG_TCON 1
#define PanelSwapRB 0
#define PanelSwap8BitML 0
#define PanelSwap6BitML 0
#define PanelDClkDelay 0
#define PanelInvDE 0
#define PanelInvDClk 0
#define PanelInvHSync 0
#define PanelInvVSync 0
// driving current setting 0==>4mA, 1==>6mA, 2==>8mA ,3==>12mA
#define PanelDCLKCurrent 1 // Dclk current
#define PanelDECurrent 1 // DE signal current
#define PANELHSCURRENT 1 // HSYNC current
#define PANELVSCURRENT 1 // VSYNC current
#define PANELBMCURRENT 1 // B data High-Nibble current
#define PANELBLCURRENT 1 // B data Low-Nibble current
#define PANELGMCURRENT 1 // G data High-Nibble current
#define PANELGLCURRENT 1 // G data Low-Nibble current
#define PANELRMCURRENT 1 // R data High-Nibble current
#define PANELRLCURRENT 1 // R data Low-Nibble current
#define PANELADCLKCURRENT 1 // Analog Panel DCLK current
#define PanelOnTiming1 100 // time between panel & data while turn on power
#define PanelOnTiming2 100 // time between data & back light while turn on power
#define PanelOffTiming1 20 // time between back light & data while turn off power
#define PanelOffTiming2 20 // time between data & panel while turn off power
#define PanelHSyncWidth 20
#define PanelHSyncBackPorch 39
#define PanelVSyncWidth 6
#define PanelVSyncBackPorch 44
#define PANEL_DE_VSTART 0
#define PanelHStart (PanelHSyncWidth+PanelHSyncBackPorch)
#define PanelVStart (PanelVSyncWidth+PanelVSyncBackPorch)
#define PanelWidth 480
#define PanelHeight 234
#define PanelHTotal 610
#define PanelVTotal 270
#define PanelVdeEnd PanelHeight+4
#define PanelVSiEnd PanelHeight+4
#define PanelMinHTotal 620
#define PanelDCLK 9.5//(((DWORD)PanelHTotal*PanelVTotal*60)/1000000/3)
///////////////////////////////////////////////////////
// TCON setting
///////////////////////////////////////////////////////
// PTC Mode setting
#define SET_PTC_MODE1 0x8E // PTC_MODE1(0xD0)
#define SET_PTC_MODE2_NOR 0x6E//0x71 // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE2_INV 0x7E // BK1_D1_PTC_MODE2(0xD1) ORG:0x18
#define SET_PTC_MODE3 0x81//0x82//0x81 // PTC_MODE3(0xD2)
// PTC Timming Setting
#define SET_FRP_TRAN 0x13 // GPO_FRP_TRAN(0xDC)
#define SET_STH_START 0x2D // GPO_STH_START(0xDD) ORG:0x2C
#define SET_STH_WIDTH 0x01 // GPO_STH_WIDTH(0xDE)
#define SET_OEH_START 0x88 // GPO_OEH_START(0xDF)
#define SET_OEH_WIDTH 0x0B // GPO_OEH_WIDTH(0xE0)
#define SET_OEV_START 0x03 // GPO_OEV_START(0xE1)
#define SET_OEV_WIDTH 0x2A // GPO_OEV_WIDTH(0xE2)
#define SET_CKV_START 0x28 // GPO_CKV_START(0xE3)
#define SET_CKV_START2 0x00 // GPO_CKV_START2(0xE4)
#define SET_CKV_WIDTH 0x2A // GPO_CKV_WIDTH(0xE5)
#define SET_STV_LINE_TH 0x42 // GPO_STV_LINE_TH(0xE6)
#define SET_STV_START 0x00 // GPO_STV_START(0xE7)
#define SET_STV_WIDTH 0x00 // GPO_STV_WIDTH(0xE8)
#define SET_OEV2_START 0x04 // GPO_OEV2_START(0xE9)
#define SET_OEV3_START 0x04 // GPO_OEV3_START(0xEA)
#define SET_H_ST_DLY_L 0x04 // H_ST_DLY_L(0xEB)
#define SET_H_ST_DLY_H 0xA4 // H_ST_DLY_H(0xEC)
#define SET_CLK_DLY_SYNC_OUT 0x00 // CLK_DLY_SYNC_OUT(0xED)
#define SET_CKV_END2 0x28 // GPO_CKV_END2(0xEE)
#define SET_Q1H 0x00 // Q1H_SETTING(0xEF)
#define SET_OEV2_WIDTH 0x80 //Disable OEV2 //0x54 // GPO_OEV2_WIDTH(0xCD)
#define SET_OEV3_WIDTH 0x80 //Disable OEV3 //0x54 // GPO_OEV3_WIDTH(0xCE)
#define SET_OEV_DELTA 0x54 // GPO_OEV_DELTA(0xCF)
// VCOM setting
#define SET_BVOM_DC 0xA5//0x8A//0xDE//0x7C //0xA0 //DEF_VCOM_DC // BVOM_DC(0x43)
#define SET_BVOM_OUT 0x6B//0x89//0x72 //0x80 //DEF_VCOM_AC // BVOM_OUT(0x44)
// DAC setting
#define SET_VDAC_ADJ1 0x07 // VADC_ADJ1(0xAA)
#define SET_VDAC_ADJ2 0x00 // VDAC_ADJ2(0xAB)
// Video decoder
#define _656_PLL_VALUE 0x67 //BK2_9D_DPL_NSPL_HIGH
#if (MST_CHIP==MST710A) //BK0_10_COCTRL1
#define COCTRL1_VALUE 0xA0
#else
#define COCTRL1_VALUE 0x20
#endif
#define SVD_EN_VALUE0 0x40 //BK2_1A_SVD_EN
#define BK1_7B_TERM_SEL_VALUE 0xE4
#define BK1_7C_CROING_VALUE 0x24
#define PANEL_SYNC_MODE_1 0
#define ENABLE_VSYNC_CTL_AUTO_H_TOTAL 1
#define ENABLE_CHECK_AUTO_H_TOTAL 1
#define ENABLE_OVER_SCAN 1
#define VD_OVER_SCAN_H 30 // 1.0%
#define VD_OVER_SCAN_V 20 // 1.0%
#define BK0_03_SYNC_Sample_Edge 0x98
#ifdef _VDCaptureSetting_
code _CaptureVideoWinType tMsVDCapture[SIG_NUMS] = // For internal VD
{
{0x37, 0x09, 640, 480}, // NSTC
{0x3D, 0x0D, 640, 576}, // PAL
{0x3C, 0x18, 640, 576}, // SECAM
{0x3d, 0x13, 640, 480}, // NTSC-443
{0x3d, 0x13, 640, 480}, // PAL-60
{0x3d, 0x13, 640, 480}, // PAL-M
{0x3C, 0x18, 640, 576}, // PAL-Nc
};
code _CaptureSvideoWinOffsetType tSvideoCaptureOffset[SIG_NUMS] = // For internal VD
{
{-0x10, 0}, // NSTC
{-0x10, 0}, // PAL
{-0x10, 0}, // SECAM
{-0x10, 0}, // NTSC-443
{-0x10, 0}, // PAL-60
{-0x10, 0}, // PAL-M
{-0x10, 0}, // PAL-Nc
};
#endif
#define FreeRunHTotal 0x280
#define PalHTotal 0x2A9
#define NtscHTotal 0x2AD
#ifdef EnableUseModeTbl
RegUnitType code tENDModeTbl[]=
{
{_END_OF_TBL_,0},
};
RegUnitType code tNtscModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_32_SRH_H,0x8C},
{BK0_31_SRH_M,0x6A},
{BK0_35_SRV_H,0x90},
{BK0_34_SRV_M,0x08},
{BK0_09_SPRVDC_L,0xDC},
{BK0_0B_SPRHDC_L,0x6A},
{BK0_27_OPL_SET2, 0x3D},
{_END_OF_TBL_, 0x00},
};
RegUnitType code tPalModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_32_SRH_H,0x8C},
{BK0_31_SRH_M,0x7F},
{BK0_0B_SPRHDC_L,0x6A},
{BK0_27_OPL_SET2, 0x39},//0x3A
{_END_OF_TBL_, 0x00},
};
RegUnitType code tFreeRunModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
/*
{BK0_44_VFDEEND_L,LOBYTE(PanelVdeEnd-02)},
{BK0_45_VFDEEND_H,HIBYTE(PanelVdeEnd-02)},
{BK0_4A_SIVEND_L,LOBYTE(PanelVSiEnd-02)},
{BK0_4B_SIVEND_H,HIBYTE(PanelVSiEnd-02)},
*/
{BK0_50_VSST_L,0xf0},
{BK0_51_VSST_H,0x08},
{_END_OF_TBL_, 0x00},
};
RegUnitType code tTVSnowModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
#if VGA_ENABLE
// 720x480i 60Hz
RegUnitType code t720_480i_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_05_SPRVST_L, 0x22},
{BK0_06_SPRVST_H, 0x00},
{BK0_07_SPRHST_L, 0x74},
{BK0_09_SPRVDC_L, 0xE2},
{BK0_0A_SPRVDC_H, 0x01},
{BK0_0B_SPRHDC_L, 0xDB},
{BK0_27_OPL_SET2, 0x3C},
{BK0_30_SRH_L, 0x00},
{BK0_31_SRH_M, 0xB9},
{BK0_32_SRH_H, 0xCA},
{BK0_33_SRV_L, 0x00},
{BK0_34_SRV_M, 0x00},
{BK0_35_SRV_H, 0x90},
{BK0_42_HFDEST_L,0x33},
{BK0_44_VFDEEND_L, 0xF0},
{BK0_48_SIHST_L, 0x3A},
{BK0_4A_SIVEND_L, 0xF0},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t640_480_VGA_ModeTbl[]=
{//Reg Vale
{BK0_00_REGBK,REG_BANK_SCALER},
{BK0_0D_LYL,0x0F},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t800_600_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
RegUnitType code t1024_768_VGA_ModeTbl[]=
{//Reg Vale
{_END_OF_TBL_, 0x00},
};
#endif
#endif
//*******************************************************************
//Ace setting
#define CbGain 0x80
#define CrGain 0x80
#define RedGain 0x80
#define GreenGain 0x80
#define BlueGain 0x80
#define INIT_VIDEO_CONTRAST_X0 60
#define INIT_VIDEO_CONTRAST_X1 70
#define INIT_VIDEO_CONTRAST_X2 85
#define INIT_VIDEO_CONTRAST_X3 90
#define INIT_VIDEO_CONTRAST_X4 95
#define INIT_VIDEO_BRIGHTNESS_X0 0x60
#define INIT_VIDEO_BRIGHTNESS_X1 0x70
#define INIT_VIDEO_BRIGHTNESS_X2 0x85
#define INIT_VIDEO_BRIGHTNESS_X3 0xB0
#define INIT_VIDEO_BRIGHTNESS_X4 0xC0
#define INIT_VIDEO_SATURATION_X0 0
#define INIT_VIDEO_SATURATION_X1 80
#define INIT_VIDEO_SATURATION_X2 135
#define INIT_VIDEO_SATURATION_X3 150
#define INIT_VIDEO_SATURATION_X4 180
#define INIT_MSVD_COMB_YGAIN 0x96//0xA0//0x80 //BK3_13
#define INIT_MSVD_COMB_CbGAIN 0x96 //BK3_14
#define INIT_MSVD_COMB_CrGAIN 0x6A //BK3_15
#define INIT_MSVD_COMB_CONTRAST 0x80//0x90//0xA0 //BK3_63
#define INIT_MSVD_COMB_BRIGHTNESS 0x93//0x8E//0x94
#define INIT_MSVD_COMB_SATURATION 0x80//0x93
#define INIT_MSVD_TV_BRIGHTNESS 0x0CE // bk2_38[6] bk2_3a[7:0] MAXVALUE=0X1FF
#ifdef EnableUseGammaTbl
BYTE code tGammaTableNormal[3][33]=
{
{
0x00,0x02,0x11,0x24,0x39,0x4A,0x58,0x62,0x6A,0x74,0x7C,
0x84,0x8A,0x90,0x96,0x9C,0xA1,0xA7,0xAC,0xB2,0xB7,0xBD,
0xC2,0xC7,0xCD,0xD2,0xD8,0xDF,0xE5,0xEC,0xF2,0xF9,0xFF,
},
{
0x00,0x02,0x11,0x24,0x39,0x4A,0x58,0x62,0x6A,0x74,0x7C,
0x84,0x8A,0x90,0x96,0x9C,0xA1,0xA7,0xAC,0xB2,0xB7,0xBD,
0xC2,0xC7,0xCD,0xD2,0xD8,0xDF,0xE5,0xEC,0xF2,0xF9,0xFF,
},
{
0x00,0x02,0x11,0x24,0x39,0x4A,0x58,0x62,0x6A,0x74,0x7C,
0x84,0x8A,0x90,0x96,0x9C,0xA1,0xA7,0xAC,0xB2,0xB7,0xBD,
0xC2,0xC7,0xCD,0xD2,0xD8,0xDF,0xE5,0xEC,0xF2,0xF9,0xFF,
},
};
#endif
#ifdef EnableColorMatrix
code short tVideoColorCorrectionMatrix[][3]=
{
0x0454,-0x0006,-0x004E,-0x0080, 0x04C8,-0x0048, 0x0010,-0x0052,
0x0442,-0x82E6, 0x4288,-0xCDBB, 0x0FA4,-0x962C, 0xDEF3,-0x5F3C,
-0x5024, 0x61BF, 0xD7EF,-0xD116, 0xA1EE, 0x752C,-0xCBBB, 0x68B1,
-0xC34B, 0x2996,-0xFE8B, 0xEBC9,-0xDC39, 0x1832,-0xD804, 0x27EE,
};
#endif
#ifdef _EnableFCC_
RegUnitType code tInitializeFCC[] =
{
/////////////////////////////////////////////////
// Initialize MACE table
/////////////////////////////////////////////////
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_56_FCC_CB_1T, 0x70}, // FCC_
{BK1_57_FCC_CR_1T, 0x9B}, // FCC_
{BK1_58_FCC_CB_2T, 0x6E}, // FCC_
{BK1_59_FCC_CR_2T, 0xAC}, // FCC_
{BK1_5A_FCC_CB_3T, 0xA5}, // FCC_
{BK1_5B_FCC_CR_3T, 0x69}, // FCC_
{BK1_5C_FCC_CB_4T, 0x5A}, // FCC_
{BK1_5D_FCC_CR_4T, 0x9A}, // FCC_
{BK1_5E_FCC_CB_5T, 0x5A}, // FCC_
{BK1_5F_FCC_CR_5T, 0x75}, // FCC_
{BK1_60_FCC_CB_6T, 0xB0}, // FCC_
{BK1_61_FCC_CR_6T, 0x48}, // FCC_
{BK1_62_FCC_CB_7T, 0x64}, // FCC_
{BK1_63_FCC_CR_7T, 0xC8}, // FCC_
{BK1_64_FCC_CB_8T, 0x80}, // FCC_
{BK1_65_FCC_CR_8T, 0x80}, // FCC_
{BK1_66_FCC_CB_9T, 0x80}, // FCC_
{BK1_67_FCC_CR_9T, 0x98},// FCC_
{BK1_68_FCC_WIN1, 0xA6}, // FCC_
{BK1_69_FCC_WIN2, 0xBA}, // FCC_
{BK1_6A_FCC_WIN3, 0xFB}, // FCC_
{BK1_6B_FCC_WIN4, 0x73}, // FCC_
{BK1_6C_FCC_WIN5, 0xFB}, // FCC_
{BK1_6D_FCC_WIN6, 0xFB}, // FCC_
{BK1_6E_FCC_WIN7, 0xFF}, // FCC_
{BK1_6F_FCC_WIN8, 0x6A}, // FCC_
{BK1_70_FCC_WIN9, 0x00}, // FCC_
{BK1_71_FCC_Y_TH, 0xFF}, // FCC_
{BK1_72_FCC_K1K2, 0x60}, // FCC_
{BK1_73_FCC_K3K4, 0xFE}, // FCC_
{BK1_74_FCC_K5K6, 0xCB}, // FCC_
{BK1_75_FCC_K7K8, 0x85}, // FCC_
// {BK1_76_FCC_CTRL, 0x2F}, // FCC_
// {BK1_77_APP_CTRL, 0x7E}, // FCC_
{BK1_78_PEAK_BAND1, 0x18}, // FCC_
{BK1_79_PEAK_BAND2, 0x58}, // FCC_
// {BK1_7A_LTI, 0x98}, // FCC_
{BK1_7D_CTI,0x78},
{BK1_7E_VIP_Y_CTRL,0x03},
{BK1_7F_MAX_PIX, 0x80}, // MAX_PIX
{BK1_80_MIN_PIX, 0x40}, // MIN_PIX
// {BK1_81_EGE_BAND1_POS,0x40},
// {BK1_82_EGE_BAND1_NEG,0x60},
// {BK1_84_EGE_BAND2_NEG,0x60},
// {BK1_85_M_BRI,0x12},//0x08},
// {BK1_86_EGE_LTI_POS,0x10},
// {BK1_87_EGE_LTI_NEG,0x20},
// {BK1_88_YC_LPF, 0x88},
{BK1_89, 0x00},
// {BK1_8A, 0x23},
{BK1_8B, 0x43},
{BK1_8C, 0xFF},
{BK1_8D, 0xAE},
{BK1_8E, 0x36},
{BK1_8F, 0x01},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
RegUnitType code tVideoFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_77_APP_CTRL, 0x7E}, // FCC_
{BK1_85_M_BRI,0x08},
//{BK1_88_YC_LPF, 0x88}, //Nelson del
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
#if VGA_ENABLE
RegUnitType code tPCFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_77_APP_CTRL, 0}, // FCC_
{BK1_85_M_BRI,0},
{BK1_88_YC_LPF, 0},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00}
};
#endif
RegUnitType code t_AVInitializeFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_76_FCC_CTRL, 0x2F}, // FCC_
{BK1_7A_LTI, 0x98}, // FCC_
{BK1_7C_CROING,0x24},
{BK1_81_EGE_BAND1_POS,0x40},
{BK1_82_EGE_BAND1_NEG,0x60},
{BK1_84_EGE_BAND2_NEG,0x60},
{BK1_86_EGE_LTI_POS,0x10},
{BK1_87_EGE_LTI_NEG,0x20},
{BK1_88_YC_LPF, 0x80},
{BK1_8A, 0x23},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
RegUnitType code t_TVInitializeFCC[] =
{
{BK0_00_REGBK, REG_BANK1_ADC_ACE_MCU},
{BK1_76_FCC_CTRL, 0x2D},
{BK1_7A_LTI, 0x90},
{BK1_7C_CROING,0x64},
{BK1_81_EGE_BAND1_POS,0x00},
{BK1_82_EGE_BAND1_NEG,0x00},
{BK1_84_EGE_BAND2_NEG,0x00},
{BK1_86_EGE_LTI_POS,0x00},
{BK1_87_EGE_LTI_NEG,0x00},
{BK1_88_YC_LPF, 0x9C},
{BK1_8A, 0x43},
{BK0_00_REGBK, REG_BANK_SCALER},
{_END_OF_TBL_, 0x00},
};
#endif // _EnableFcc_
#endif
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