reg_nsr = ior(db,0x1);			if(reg_nsr & 0x80)				db->Speed =10;			else				db->Speed =100;			break;		}		i++;		mdelay(1);	}while(i<3000);	/* wait 3 second  */	//printk("i=%d  Speed=%d\n",i,db->Speed);		/* set and active a timer process */	init_timer(&db->timer);	db->timer.expires 	= DMFE_TIMER_WUT * 2;	db->timer.data 		= (unsigned long)dev;	db->timer.function 	= &dmfe_timer;	add_timer(&db->timer);	//Move to DM9000 initiallization was finished. 		netif_start_queue(dev);	return 0;}/* Set PHY operationg mode*/static void set_PHY_mode(board_info_t *db){	u16 phy_reg0 = 0x1200;		/* Auto-negotiation & Restart Auto-negotiation */	u16 phy_reg4 = 0x01e1;		/* Default flow control disable*/	if ( !(db->op_mode & DM9KS_AUTO) ) // op_mode didn't auto sense */	{ 		switch(db->op_mode) {			case DM9KS_10MHD:  phy_reg4 = 0x21;                         	           phy_reg0 = 0x1000;					   break;			case DM9KS_10MFD:  phy_reg4 = 0x41; 					   phy_reg0 = 0x1100;                                	   break;			case DM9KS_100MHD: phy_reg4 = 0x81; 					   phy_reg0 = 0x3000;				    	   break;			case DM9KS_100MFD: phy_reg4 = 0x101; 					   phy_reg0 = 0x3100;				   	   break;			default: 					   break;		} // end of switch	} // end of if	phy_write(db, 0, phy_reg0);	phy_write(db, 4, phy_reg4);}/* 	Initilize dm9000 board*/static void dmfe_init_dm9000(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	DMFE_DBUG(0, "dmfe_init_dm9000()", 0);	/* set the internal PHY power-on, GPIOs normal, and wait 2ms */	iow(db, DM9KS_GPR, 1); 	/* Power-Down PHY */	udelay(500);	iow(db, DM9KS_GPR, 0);	/* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */	udelay(20);		/* wait 2ms for PHY power-on ready */	/* do a software reset and wait 20us */	iow(db, DM9KS_NCR, 3);	udelay(20);		/* wait 20us at least for software reset ok */	iow(db, DM9KS_NCR, 3);	/* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on */	udelay(20);		/* wait 20us at least for software reset ok */	iow(db, DM9KS_PIN_C, 0); 	/* int pin is high */	udelay(20);     iow(db, DM9KS_NCR, 0);	/* I/O mode */	db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */	/* Set PHY */	db->op_mode = media_mode;	set_PHY_mode(db);	/* Program operating register */	iow(db, DM9KS_NCR, 0);	iow(db, DM9KS_TCR, 0);		/* TX Polling clear */	iow(db, DM9KS_BPTR, 0x3f);	/* Less 3kb, 600us */	iow(db, DM9KS_SMCR, 0);		/* Special Mode */	iow(db, DM9KS_NSR, 0x2c);	/* clear TX status */	iow(db, DM9KS_ISR, 0x0f); 	/* Clear interrupt status */	/* Added by jackal at 03/29/2004 */#if defined(CHECKSUM)	iow(db, DM9KS_TCCR, 0x07);	/* TX UDP/TCP/IP checksum enable */	iow(db, DM9KS_RCSR, 0x02);	/*Receive checksum enable */#endif#if defined(ETRANS)	iow(db, DM9KS_ETXCSR, 0x83);#endif 	/* Set address filter table */	dm9000_hash_table(dev);	/* Activate DM9000A/DM9010 */	iow(db, DM9KS_RXCR, DM9KS_REG05 | 1);	/* RX enable */	iow(db, DM9KS_IMR, DM9KS_REGFF); 	// Enable TX/RX interrupt mask 	/* Init Driver variable */	db->tx_pkt_cnt 		= 0;			netif_carrier_on(dev);	spin_lock_init(&db->lock);}/*  Hardware start transmission.  Send a packet to media from the upper layer.*/static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	char * data_ptr;	int i, tmplen,iorread;	if(db->Speed == 10)		{if (db->tx_pkt_cnt >= 1) return 1;}	else		{if (db->tx_pkt_cnt >= 2) return 1;}		/* packet counting */	db->tx_pkt_cnt++;	db->stats.tx_packets++;	db->stats.tx_bytes+=skb->len;	if (db->Speed == 10)		{if (db->tx_pkt_cnt >= 1) netif_stop_queue(dev);}	else		{if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev);}	/* Disable all interrupt */	iow(db, DM9KS_IMR, DM9KS_DISINTR);	/* Set TX length to reg. 0xfc & 0xfd */	iow(db, DM9KS_TXPLL, (skb->len & 0xff));	iow(db, DM9KS_TXPLH, (skb->len >> 8) & 0xff);	/* Move data to TX SRAM */	data_ptr = (char *)skb->data;		DM9000_outb(DM9KS_MWCMD, db->io_addr); // Write data into SRAM trigger	//switch(db->io_mode)	//{		//case DM9KS_BYTE_MODE:			//for (i = 0; i < skb->len; i++)				//DM9000_outb((data_ptr[i] & 0xff), db->io_data);			//break;		//case DM9KS_WORD_MODE:			tmplen = (skb->len + 1) / 2;			for (i = 0; i < tmplen; i++)         			DM9000_outw(((u16 *)data_ptr)[i], db->io_data);			printk(KERN_ERR"db->io_data is %c\n", db->io_data);			printk(KERN_ERR"START X \n");			         		//break;         	//case DM9KS_DWORD_MODE:         		//tmplen = (skb->len + 3) / 4;						//for (i = 0; i< tmplen; i++)				//DM9000_outl(((u32 *)data_ptr)[i], db->io_data);			//break;	//}	#if !defined(ETRANS)	/* Issue TX polling command */	iow(db, DM9KS_TCR, 0x1); /* Cleared after TX complete*/#endif	/* Saved the time stamp */	dev->trans_start = jiffies;	db->cont_rx_pkt_cnt =0;	/* Free this SKB */	dev_kfree_skb(skb);	/* Re-enable interrupt */	iow(db, DM9KS_IMR, DM9KS_REGFF);      iorread=ior(db, 0x04);		/*transmit status   register */      printk(KERN_ERR"IORREAD=:%x\n",iorread);	  	return 0;}/*  Stop the interface.  The interface is stopped when it is brought.*/static int dmfe_stop(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	DMFE_DBUG(0, "dmfe_stop", 0);	/* deleted timer */	del_timer(&db->timer);	netif_stop_queue(dev); 	/* free interrupt */	free_irq(dev->irq, dev);	/* RESET devie */	phy_write(db, 0x00, 0x8000);	/* PHY RESET */	iow(db, DM9KS_GPR, 0x01); 	/* Power-Down PHY */	iow(db, DM9KS_IMR, DM9KS_DISINTR);	/* Disable all interrupt */	iow(db, DM9KS_RXCR, 0x00);	/* Disable RX */	/* Dump Statistic counter */#if FALSE	printk("\nRX FIFO OVERFLOW %lx\n", db->stats.rx_fifo_errors);	printk("RX CRC %lx\n", db->stats.rx_crc_errors);	printk("RX LEN Err %lx\n", db->stats.rx_length_errors);	printk("RESET %x\n", db->reset_counter);	printk("RESET: TX Timeout %x\n", db->reset_tx_timeout);	printk("g_TX_nsr %x\n", g_TX_nsr);#endif	return 0;}static void dmfe_tx_done(unsigned long unused){	struct net_device *dev = dmfe_dev;	board_info_t *db = (board_info_t *)dev->priv;	int  nsr;	DMFE_DBUG(0, "dmfe_tx_done()", 0);		nsr = ior(db, DM9KS_NSR);	if(nsr & 0x04) db->tx_pkt_cnt--;	if(nsr & 0x08) db->tx_pkt_cnt--;	if (db->tx_pkt_cnt < 0)	{		printk("[dmfe_tx_done] tx_pkt_cnt ERROR!!\n");		db->tx_pkt_cnt =0;	}	if (db->Speed == 10)		{if(db->tx_pkt_cnt < 1 ) netif_wake_queue(dev);}	else				{if(db->tx_pkt_cnt < 2 ) netif_wake_queue(dev);}printk(KERN_ERR"TEST if dmfe_fx_done is working right,if you see it ,it working right\n");	return;}/*  DM9000 insterrupt handler  receive the packet to upper layer, free the transmitted packet*/#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)#elsestatic irqreturn_t dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)#endif{	struct net_device *dev = dev_id;	board_info_t *db;	int int_status,i;	u8 reg_save;	DMFE_DBUG(0, "dmfe_interrupt()", 0);	/* A real interrupt coming */	db = (board_info_t *)dev->priv;	spin_lock(&db->lock);	/* Save previous register address */	reg_save = DM9000_inb(db->io_addr);	/* Disable all interrupt */	iow(db, DM9KS_IMR, DM9KS_DISINTR); 	/* Got DM9000A/DM9010 interrupt status */	int_status = ior(db, DM9KS_ISR);		/* Got ISR */	iow(db, DM9KS_ISR, int_status);		/* Clear ISR status */ 	/* Link status change */	if (int_status & DM9KS_LINK_INTR) 	{		netif_stop_queue(dev);		for(i=0; i<500; i++) /*wait link OK, waiting time =0.5s */		{			phy_read(db,0x1);			if(phy_read(db,0x1) & 0x4) /*Link OK*/			{				/* wait for detected Speed */				for(i=0; i<200;i++)					udelay(1000);				/* set media speed */				if(phy_read(db,0)&0x2000) db->Speed =100;				else db->Speed =10;				break;			}			udelay(1000);		}		netif_wake_queue(dev);		//printk("[INTR]i=%d speed=%d\n",i, (int)(db->Speed));		}	/* Received the coming packet */	if (int_status & DM9KS_RX_INTR) 		dmfe_packet_receive(dev);	/* Trnasmit Interrupt check */	if (int_status & DM9KS_TX_INTR)		dmfe_tx_done(0);		if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)	{		iow(db, DM9KS_IMR, 0xa2);	}	else	{		/* Re-enable interrupt mask */ 		iow(db, DM9KS_IMR, DM9KS_REGFF);	}		/* Restore previous register address */	DM9000_outb(reg_save, db->io_addr); printk(KERN_ERR"interrup in dmfe \n");	spin_unlock(&db->lock); #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)	return IRQ_HANDLED;#endif}/*  Get statistics from driver.*/static struct net_device_stats * dmfe_get_stats(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	DMFE_DBUG(0, "dmfe_get_stats", 0);	return &db->stats;}/*  Process the upper socket ioctl command*/static int dmfe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd){	DMFE_DBUG(0, "dmfe_do_ioctl()", 0);	return 0;}/* Our watchdog timed out. Called by the networking layer */static voiddmfe_timeout(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	DMFE_DBUG(0, "dmfe_TX_timeout()", 0);	printk("TX time-out -- dmfe_timeout().\n");	db->reset_tx_timeout++;	db->stats.tx_errors++;#if FALSE	printk("TX packet count = %d\n", db->tx_pkt_cnt);		printk("TX timeout = %d\n", db->reset_tx_timeout);		printk("22H=0x%02x  23H=0x%02x\n",ior(db,0x22),ior(db,0x23));	printk("faH=0x%02x  fbH=0x%02x\n",ior(db,0xfa),ior(db,0xfb));#endif	dmfe_reset(dev);	}static void dmfe_reset(struct net_device * dev){	board_info_t *db = (board_info_t *)dev->priv;	u8 reg_save;	int i;	/* Save previous register address */	reg_save = DM9000_inb(db->io_addr);	netif_stop_queue(dev); 	db->reset_counter++;	dmfe_init_dm9000(dev);		db->Speed =10;	for(i=0; i<1000; i++) /*wait link OK, waiting time=1 second */	{		if(phy_read(db,0x1) & 0x4) /*Link OK*/		{			if(phy_read(db,0)&0x2000) db->Speed =100;			else db->Speed =10;			break;		}		udelay(1000);	}		netif_wake_queue(dev);		/* Restore previous register address */	DM9000_outb(reg_save, db->io_addr);}/*  A periodic timer routine*/static void dmfe_timer(unsigned long data){	struct net_device * dev = (struct net_device *)data;