board_info_t *db = (board_info_t *)dev->priv;	DMFE_DBUG(0, "dmfe_timer()", 0);		if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)	{		db->cont_rx_pkt_cnt=0;		iow(db, DM9KS_IMR, DM9KS_REGFF);	}	/* Set timer again */	db->timer.expires = DMFE_TIMER_WUT;	add_timer(&db->timer);		return;}#if !defined(CHECKSUM)#define check_rx_ready(a)	((a) == 0x01)#elseinline u8 check_rx_ready(u8 rxbyte){	if (!(rxbyte & 0x01))		return 0;	return ((rxbyte >> 4) | 0x01);}#endif/*  Received a packet and pass to upper layer*/static void dmfe_packet_receive(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	struct sk_buff *skb;	u8 rxbyte, val;	u16 i, GoodPacket, tmplen = 0, MDRAH, MDRAL;	u32 tmpdata;	rx_t rx;	u16 * ptr = (u16*)&rx;	u8* rdptr;	DMFE_DBUG(0, "dmfe_packet_receive()", 0);	do {		/*store the value of Memory Data Read address register*/		MDRAH=ior(db, DM9KS_MDRAH);		MDRAL=ior(db, DM9KS_MDRAL);				ior(db, DM9KS_MRCMDX);		/* Dummy read */		rxbyte = DM9000_inb(db->io_data);	/* Got most updated data */		/* packet ready to receive check */		if(!(val = check_rx_ready(rxbyte))) break;		/* A packet ready now  & Get status/length */		GoodPacket = TRUE;		DM9000_outb(DM9KS_MRCMD, db->io_addr);		/* Read packet status & length */		switch (db->io_mode) 			{			  case DM9KS_BYTE_MODE:  				    *ptr = DM9000_inb(db->io_data) + 				               (DM9000_inb(db->io_data) << 8);				    *(ptr+1) = DM9000_inb(db->io_data) + 					    (DM9000_inb(db->io_data) << 8);				    break;			  case DM9KS_WORD_MODE:				    *ptr = DM9000_inw(db->io_data);				    *(ptr+1)    = DM9000_inw(db->io_data);				    break;			  case DM9KS_DWORD_MODE:				    tmpdata  = DM9000_inl(db->io_data);				    *ptr = tmpdata;				    *(ptr+1)    = tmpdata >> 16;				    break;			  default:				    break;			}		/* Packet status check */		if (rx.desc.status & 0xbf)		{			GoodPacket = FALSE;			if (rx.desc.status & 0x01) 			{				db->stats.rx_fifo_errors++;				printk("<RX FIFO error>\n");			}			if (rx.desc.status & 0x02) 			{				db->stats.rx_crc_errors++;				printk("<RX CRC error>\n");			}			if (rx.desc.status & 0x80) 			{				db->stats.rx_length_errors++;				printk("<RX Length error>\n");			}			if (rx.desc.status & 0x08)				printk("<Physical Layer error>\n");		}printk(KERN_ERR"TEST if dmfe_packet_receive is used by dmfe interrupt function,if you see it ,it working right\n");printk(KERN_ERR"GoodPacket true or fault :%d\n",GoodPacket);		if (!GoodPacket)		{			// drop this packet!!!			switch (db->io_mode)			{				case DM9KS_BYTE_MODE:			 		for (i=0; i<rx.desc.length; i++)						DM9000_inb(db->io_data);					break;				case DM9KS_WORD_MODE:					tmplen = (rx.desc.length + 1) / 2;					for (i = 0; i < tmplen; i++)						DM9000_inw(db->io_data);					break;				case DM9KS_DWORD_MODE:					tmplen = (rx.desc.length + 3) / 4;					for (i = 0; i < tmplen; i++)						DM9000_inl(db->io_data);					break;			}			continue;/*next the packet*/		}				skb = dev_alloc_skb(rx.desc.length+4);		if (skb == NULL )		{				printk(KERN_INFO "%s: Memory squeeze.\n", dev->name);			/*re-load the value into Memory data read address register*/			iow(db,DM9KS_MDRAH,MDRAH);			iow(db,DM9KS_MDRAL,MDRAL);			return;		}		else		{			/* Move data from DM9000 */			skb->dev = dev;			skb_reserve(skb, 2);			rdptr = (u8*)skb_put(skb, rx.desc.length - 4);						/* Read received packet from RX SARM */			switch (db->io_mode)			{				case DM9KS_BYTE_MODE:			 		for (i=0; i<rx.desc.length; i++)						rdptr[i]=DM9000_inb(db->io_data);					break;				case DM9KS_WORD_MODE:					tmplen = (rx.desc.length + 1) / 2;					for (i = 0; i < tmplen; i++)						((u16 *)rdptr)[i] = DM9000_inw(db->io_data);					break;				case DM9KS_DWORD_MODE:					tmplen = (rx.desc.length + 3) / 4;					for (i = 0; i < tmplen; i++)						((u32 *)rdptr)[i] = DM9000_inl(db->io_data);					break;			}					/* Pass to upper layer */			skb->protocol = eth_type_trans(skb,dev);#if defined(CHECKSUM)			if (val == 0x01)				skb->ip_summed = CHECKSUM_UNNECESSARY;#endif			netif_rx(skb);			dev->last_rx=jiffies;			db->stats.rx_packets++;			db->stats.rx_bytes += rx.desc.length;			db->cont_rx_pkt_cnt++;							if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT)			{				dmfe_tx_done(0);				break;			}		}				}while((rxbyte & 0x01) == DM9KS_PKT_RDY);	DMFE_DBUG(0, "[END]dmfe_packet_receive()", 0);	}/*  Read a word data from SROM*/static u16 read_srom_word(board_info_t *db, int offset){	iow(db, DM9KS_EPAR, offset);	iow(db, DM9KS_EPCR, 0x4);	udelay(200);	iow(db, DM9KS_EPCR, 0x0);	return (ior(db, DM9KS_EPDRL) + (ior(db, DM9KS_EPDRH) << 8) );}/*  Set DM9000A/DM9010 multicast address*/static void dm9000_hash_table(struct net_device *dev){	board_info_t *db = (board_info_t *)dev->priv;	struct dev_mc_list *mcptr = dev->mc_list;	int mc_cnt = dev->mc_count;	u32 hash_val;	u16 i, oft, hash_table[4];	DMFE_DBUG(0, "dm9000_hash_table()", 0);	/* Set Node address */	for (i = 0, oft = 0x10; i < 6; i++, oft++)		iow(db, oft, dev->dev_addr[i]);	/* Clear Hash Table */	for (i = 0; i < 4; i++)		hash_table[i] = 0x0;	/* broadcast address */	hash_table[3] = 0x8000;	/* the multicast address in Hash Table : 64 bits */	for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {		hash_val = cal_CRC((char *)mcptr->dmi_addr, 6, 0) & 0x3f; 		hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);	}	/* Write the hash table to MAC MD table */	for (i = 0, oft = 0x16; i < 4; i++) {		iow(db, oft++, hash_table[i] & 0xff);		iow(db, oft++, (hash_table[i] >> 8) & 0xff);	}}/*  Calculate the CRC valude of the Rx packet  flag = 1 : return the reverse CRC (for the received packet CRC)         0 : return the normal CRC (for Hash Table index)*/static unsigned long cal_CRC(unsigned char * Data, unsigned int Len, u8 flag){		u32 crc = ether_crc_le(Len, Data);	if (flag) 		return ~crc;			return crc;	 }/*   Read a byte from I/O port*/static u8 ior(board_info_t *db, int reg){	DM9000_outb(reg, db->io_addr);	return DM9000_inb(db->io_data);}/*   Write a byte to I/O port*/static void iow(board_info_t *db, int reg, u8 value){	DM9000_outb(reg, db->io_addr);	DM9000_outb(value, db->io_data);}/*   Read a word from phyxcer*/static u16 phy_read(board_info_t *db, int reg){	/* Fill the phyxcer register into REG_0C */	iow(db, DM9KS_EPAR, DM9KS_PHY | reg);	iow(db, DM9KS_EPCR, 0xc); 	/* Issue phyxcer read command */	udelay(100);			/* Wait read complete */	iow(db, DM9KS_EPCR, 0x0); 	/* Clear phyxcer read command */	/* The read data keeps on REG_0D & REG_0E */	return ( ior(db, DM9KS_EPDRH) << 8 ) | ior(db, DM9KS_EPDRL);	}/*   Write a word to phyxcer*/static void phy_write(board_info_t *db, int reg, u16 value){	/* Fill the phyxcer register into REG_0C */	iow(db, DM9KS_EPAR, DM9KS_PHY | reg);	/* Fill the written data into REG_0D & REG_0E */	iow(db, DM9KS_EPDRL, (value & 0xff));	iow(db, DM9KS_EPDRH, ( (value >> 8) & 0xff));	iow(db, DM9KS_EPCR, 0xa);	/* Issue phyxcer write command */	udelay(500);			/* Wait write complete */	iow(db, DM9KS_EPCR, 0x0);	/* Clear phyxcer write command */}//#ifdef MODULEMODULE_LICENSE("GPL");MODULE_DESCRIPTION("Davicom DM9000A/DM9010 ISA/uP Fast Ethernet Driver");MODULE_PARM(mode, "i");MODULE_PARM(irq, "i");MODULE_PARM(iobase, "i");MODULE_PARM_DESC(mode,"Media Speed, 0:10MHD, 1:10MFD, 4:100MHD, 5:100MFD");MODULE_PARM_DESC(irq,"EtherLink IRQ number");MODULE_PARM_DESC(iobase, "EtherLink I/O base address");/* Description:    when user used insmod to add module, system invoked init_module()   to initilize and register.*/static void  at91_dm9k_init(void){   printk(KERN_ERR "at91_dm9k_init is begin \n");      //AT91_SYS2->EBI_CSA=0x0; //CSA5   printk(KERN_ERR "at91_dm9k_init one words \n");	/* force poweron defaults for these pins ... */	//(void) at91_set_A_periph(AT91_PIN_PC9, 0);	//at91_set_gpio_value_c(AT91_PIN_PC9,0)  /* A25/CFRNW */	//(void) at91_set_A_periph(AT91_PIN_PC10, 0);	AT91_SYS->PIOA_PER=(AT91_SYS->PIOA_PER)|(0x8);	//irq5 pioa3AT91_SYS->PIOA_BSR=(AT91_SYS->PIOA_BSR)|(0x8);AT91_SYS->PIOA_PDR=(AT91_SYS->PIOA_PDR)|(0x8);AT91_SYS->PIOC_PER=((AT91_SYS->PIOC_PER)|((unsigned int) 1 << 11));	/* NCS5 */AT91_SYS->PIOC_OER=((AT91_SYS->PIOC_OER)|((unsigned int) 1 << 11));AT91_SYS->PIOC_CODR=(AT91_SYS->PIOC_CODR)|((unsigned int) 0<< 11);	//at91_set_gpio_value_c(AT91_PIN_PC6,1)/*  nWAIT */ AT91_SYS->EBI_SMC2_CSR[5]=(AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_16 | AT91C_SMC2_BAT | AT91C_SMC2_WSEN				| AT91C_SMC2_NWS						| AT91C_SMC2_RWSETUP						| AT91C_SMC2_RWHOLD);	//AT91_SYS->AIC_SMR[30]=0x40;AT91_SYS->AIC_SMR[30]=0x40;      printk(KERN_ERR "at91_dm9k_init is finish \n");}static int __init init_module(void){       at91_dm9k_init();	switch(mode) {		case DM9KS_10MHD:		case DM9KS_100MHD:		case DM9KS_10MFD:		case DM9KS_100MFD:			media_mode = mode;			break;		default:			media_mode = DM9KS_AUTO;	}	dmfe_dev = dmfe_probe1();		if(IS_ERR(dmfe_dev))		return PTR_ERR(dmfe_dev);	return 0;}/* Description:    when user used rmmod to delete module, system invoked clean_module()   to  un-register DEVICE.*/static void __exit cleanup_module(void){	struct net_device *dev = dmfe_dev;	DMFE_DBUG(0, "clean_module()", 0);	unregister_netdev(dmfe_dev);	release_mem_region(dev->base_addr, 0x100);#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)	kfree(dev);#else	free_netdev(dev);#endif		DMFE_DBUG(0, "clean_module() exit", 0);}//#endifmodule_init(init_module);module_exit(cleanup_module);