?? vectors.asm
字號:
;-----------------------------------------------------
.def Interrupt_Vectors
; .ref nNMI_SINT16
; .ref SINT17
; .ref SINT18
; .ref SINT19
; .ref SINT20
; .ref SINT21
; .ref SINT22
; .ref SINT23
; .ref SINT24
; .ref SINT25
; .ref SINT26
; .ref SINT27
; .ref SINT28
; .ref SINT29
; .ref SINT30
; .ref _ExtInt0
.ref _int1
; .ref _Tint0
; .ref BRINT0_SINT4
; .ref BXINT0_SINT5
; .ref _Tint1
; .ref _ExtInt3
.ref _mcbsp1_read
.ref _mcbsp1_write
; .ref _ExtInt2
.ref _c_int00
;*****************************************************
STACK_LEN .set 100
STACK .usect "STK",STACK_LEN
;*******************************************************
.sect ".vectors"
.align 0x80 ; must be aligned on page boundary
;****************************************
; the Interrutp table see spru13lg:P182
;**************************************
Interrupt_Vectors:
nRS_SINTR: ;Reset Interrupt vector(vector_base + 0x00)
stm #STACK+STACK_LEN,SP
b _c_int00
nNMI_SINT16: ;Non-maskable Interrupt Vector (vector_base + 0x04)
;b nNMI_SINT16
rete
nop
nop ;
nop ;
SINT17: ;Software Interrupt 17 Vector (vector_base + 0x08)
;b SINT17 ; context switch
rete
nop
nop ;
nop ;
SINT18: ;Software Interrupt 18 Vector (vector_base + 0x0C)
;b SINT18
rete
nop
nop ;
nop ;
SINT19: ;Software Interrupt 19 Vector (vector_base + 0x10)
;b SINT19
rete
nop
nop ;
nop ;
SINT20: ;Software Interrupt 20 Vector (vector_base + 0x14)
;b SINT20
rete
nop
nop ;
nop ;
SINT21: ;Software Interrupt 21 Vector (vector_base + 0x18)
;b SINT21
rete
nop
nop ;
nop ;
SINT22: ;Software Interrupt 22 Vector (vector_base + 0x1C)
;b SINT22
rete
nop
nop ;
nop ;
SINT23: ;Software Interrupt 23 Vector (vector_base + 0x20)
;b SINT23
rete
nop
nop ;
nop ;
SINT24: ;Software Interrupt 24 Vector (vector_base + 0x24)
;b SINT24
rete
nop
nop ;
nop ;
SINT25: ;Software Interrupt 25 Vector (vector_base + 0x28)
;b SINT25
rete
nop
nop ;
nop ;
SINT26: ;Software Interrupt 26 Vector (vector_base + 0x2C)
;b SINT26
rete
nop
nop ;
nop ;
SINT27: ;Software Interrupt 27 Vector (vector_base + 0x30)
;b SINT27
rete
nop
nop ;
nop ;
SINT28: ;Software Interrupt 28 Vector (vector_base + 0x34)
;b SINT28
rete
nop
nop ;
nop ;
SINT29: ;Software Interrupt 29 Vector (vector_base + 0x38)
;b SINT29
rete
nop
nop ;
nop ;
SINT30: ;Software Interrupt 30 Vector (vector_base + 0x3C)
;b SINT30
rete
nop
nop ;
nop ;
nINT0_SINT0: ;External Interrupt 0 Vector (vector_base + 0x40)
b _int1
;rete
;nop
nop ;
nop
nINT1_SINT1: ;External Interrupt 1 Vector (vector_base + 0x44)
;b _ExtInt1
rete
nop
nop
nop
nINT2_SINT2: ;External Interrupt 2 Vector (vector_base + 0x48)
;b _ExtInt2
rete
nop
nop
nop
TINT0_SINT3: ;Timer Interrupt Vector (vector_base + 0x4C)
;b _Tint0
rete
nop
nop
nop
BRINT0_SINT4: ;McBSP #0 receive Interupt Vector(vector_base + 0x50)
;b BRINT0_SINT4
rete
nop
nop ;
nop
BXINT0_SINT5: ;McBSP #0 transmit Interupt Vector(vector_base + 0x54)
;b BXINT0_SINT5
rete
nop
nop ;
nop
DMAC0_SINT6: ;DMA channel 0 Interupt Vector (vector_base + 0x58)
rete
nop
nop
nop
TINT1_DMAC1_SINT7: ;Timer1 or DMA channel 1 Interupt Vector(vector_base + 0x5C)
;b _Tint1
rete
nop
nop
nop
nINT3_SINT8: ;External Interupt 3 Vector (vector_base + 0x60)
;b _ExtInt3
rete
nop
nop
nop
HPINT_SINT9: ;HPI interrupt
rete
nop
nop
nop
BRINT1_DMAC2_SINT10: ;McBSP #1 receive or DMA2 interrupt
nop
nop
b _mcbsp1_read
BXINT1_DMAC3_SINT11: ;McBSP #1 transmit or DMA3 interrupt
nop
nop
b _mcbsp1_write
DMAC4_SINT12: ;DMA channel 4
rete
nop
nop
nop
DMAC5_SINT13:
rete
nop
nop
nop
RESERVED .space 8*16
.end
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