/* * linux/arch/mips/jzsoc/common/jz_dpm.c * * JzSOC-specific DPM support * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. * * Copyright 2005 Ingenic Technology Corporation *      Wei Jianli <jlwei@ingenic.cn> * Copyright (C) 2002 MontaVista Software <source@mvista.com>. * 	Matthew Locke <mlocke@mvista.com> */#include <linux/config.h>#include <linux/dpm.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/kmod.h>#include <linux/module.h>#include <linux/proc_fs.h>#include <linux/stat.h>#include <linux/string.h>#include <linux/delay.h>#include <asm/hardirq.h>#include <asm/page.h>#include <asm/processor.h>#include <asm/uaccess.h>#include <asm/jzsoc.h>#include <linux/device.h>struct dpm_bd dpm_bd;struct dpm_md dpm_md;extern void eth_dpm_freq_pre(void);extern void eth_dpm_freq_post(void);/* Saved the boot-time parameters */static struct {	/* SDRAM parameters */	unsigned int mclk;  /* memory clock, KHz */	unsigned int tras;  /* RAS pulse width, cycles of mclk */	unsigned int rcd;   /* RAS to CAS Delay, cycles of mclk */	unsigned int tpc;   /* RAS Precharge time, cycles of mclk */	unsigned int trwl;  /* Write Precharge Time, cycles of mclk */	unsigned int trc;   /* RAS Cycle Time, cycles of mclk */	unsigned int rtcor; /* Refresh Time Constant */	unsigned int sdram_initialized;	/* LCD parameters */	unsigned int lcd_clk;    /* LCD clock, Hz */	unsigned int lcdpix_clk; /* LCD Pixel clock, Hz */	unsigned int lcd_clks_initialized;} boot_config;extern struct sys_clock jz_clocks;static void jz_update_clocks(void){	/* Next clocks must be updated if we have changed 	 * the PLL or divisors.	 */	jz_clocks.iclk = __cpm_get_iclk();	jz_clocks.sclk = __cpm_get_sclk();	jz_clocks.mclk = __cpm_get_mclk();	jz_clocks.pclk = __cpm_get_pclk();	jz_clocks.lcdclk = __cpm_get_lcdclk();	jz_clocks.pixclk = __cpm_get_pixclk();}static void jz_update_dram_rtcor(unsigned int new_mclk){	unsigned int rtcor;		new_mclk /= 1000;	rtcor = boot_config.rtcor * new_mclk / boot_config.mclk;	rtcor--;	if (rtcor < 1) rtcor = 1;	if (rtcor > 255) rtcor = 255;	REG_EMC_RTCOR = rtcor;	REG_EMC_RTCNT = rtcor;}static void jz_update_dram_dmcr(unsigned int new_mclk){	unsigned int dmcr;	unsigned int tras, rcd, tpc, trwl, trc;	unsigned int valid_time, new_time; /* ns */	new_mclk /= 1000;	tras = boot_config.tras * new_mclk / boot_config.mclk;	rcd = boot_config.rcd * new_mclk / boot_config.mclk;	tpc = boot_config.tpc * new_mclk / boot_config.mclk;	trwl = boot_config.trwl * new_mclk / boot_config.mclk;	trc = boot_config.trc * new_mclk / boot_config.mclk;	/* Validation checking */	valid_time = (boot_config.tras * 1000000) / boot_config.mclk;	new_time = (tras * 1000000) / new_mclk;	if (new_time < valid_time) tras += 1;	valid_time = (boot_config.rcd * 1000000) / boot_config.mclk;	new_time = (rcd * 1000000) / new_mclk;	if (new_time < valid_time) rcd += 1;	valid_time = (boot_config.tpc * 1000000) / boot_config.mclk;	new_time = (tpc * 1000000) / new_mclk;	if (new_time < valid_time) tpc += 1;	valid_time = (boot_config.trwl * 1000000) / boot_config.mclk;	new_time = (trwl * 1000000) / new_mclk;	if (new_time < valid_time) trwl += 1;	valid_time = (boot_config.trc * 1000000) / boot_config.mclk;	new_time = (trc * 1000000) / new_mclk;	if (new_time < valid_time) trc += 2;	tras = (tras < 4) ? 4: tras;	tras = (tras > 11) ? 11: tras;	tras -= 4;	rcd = (rcd < 1) ? 1: rcd;	rcd = (rcd > 4) ? 4: rcd;	rcd -= 1;	tpc = (tpc < 1) ? 1: tpc;	tpc = (tpc > 8) ? 8: tpc;	tpc -= 1;	trwl = (trwl < 1) ? 1: trwl;	trwl = (trwl > 4) ? 4: trwl;	trwl -= 1;	trc = (trc < 1) ? 1: trc;	trc = (trc > 15) ? 15: trc;	trc /= 2;		dmcr = REG_EMC_DMCR;		dmcr &= ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK | EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK);	dmcr |= ((tras << EMC_DMCR_TRAS_BIT) | (rcd << EMC_DMCR_RCD_BIT) | (tpc << EMC_DMCR_TPC_BIT) | (trwl << EMC_DMCR_TRWL_BIT) | (trc << EMC_DMCR_TRC_BIT));	REG_EMC_DMCR = dmcr;}static void jz_update_dram_prev(unsigned int cur_mclk, unsigned int new_mclk){		/* No risk, no fun: run with interrupts on! */	if (new_mclk > cur_mclk) {		/* We're going FASTER, so first update TRAS, RCD, TPC, TRWL		 * and TRC of DMCR before changing the frequency.		 */		jz_update_dram_dmcr(new_mclk);	} else {		/* We're going SLOWER: first update RTCOR value		 * before changing the frequency.		 */		jz_update_dram_rtcor(new_mclk);	}}static void jz_update_dram_post(unsigned int cur_mclk, unsigned int new_mclk){		/* No risk, no fun: run with interrupts on! */	if (new_mclk > cur_mclk) {		/* We're going FASTER, so update RTCOR		 * after changing the frequency 		 */		jz_update_dram_rtcor(new_mclk);	} else {		/* We're going SLOWER: so update TRAS, RCD, TPC, TRWL		 * and TRC of DMCR after changing the frequency.		 */		jz_update_dram_dmcr(new_mclk);	}}static void jz_scale_divisors(struct dpm_regs *regs){	unsigned int cfcr;	unsigned int cur_mclk, new_mclk;	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};	cfcr = REG_CPM_CFCR;	cfcr &= ~((unsigned long)regs->cfcr_mask);	cfcr |= regs->cfcr;	cfcr |= CPM_CFCR_UPE;       /* update immediately */		cur_mclk = __cpm_get_mclk();	new_mclk = __cpm_get_pllout() / div[(cfcr & CPM_CFCR_MFR_MASK) >> CPM_CFCR_MFR_BIT];	/* Update some DRAM parameters before changing frequency */	jz_update_dram_prev(cur_mclk, new_mclk);	/* Update divisores */	REG_CPM_CFCR = cfcr;	/* Update some other DRAM parameters after changing frequency */	jz_update_dram_post(cur_mclk, new_mclk);}/* Maintain the LCD clock and pixel clock */static void jz_scale_lcd_divisors(struct dpm_regs *regs){		unsigned int new_pll, new_lcd_div, new_lcdpix_div;	unsigned int cfcr;	if (!boot_config.lcd_clks_initialized) return;	new_pll = __cpm_get_pllout();	new_lcd_div = new_pll / boot_config.lcd_clk;	new_lcdpix_div = new_pll / boot_config.lcdpix_clk;	if (new_lcd_div < 1)		new_lcd_div = 1;	if (new_lcd_div > 16)		new_lcd_div = 16;	if (new_lcdpix_div < 1)		new_lcdpix_div = 1;	if (new_lcdpix_div > 512)		new_lcdpix_div = 512;	REG_CPM_CFCR2 = new_lcdpix_div - 1;	cfcr = REG_CPM_CFCR;	cfcr &= ~CPM_CFCR_LFR_MASK;	cfcr |= ((new_lcd_div - 1) << CPM_CFCR_LFR_BIT);	cfcr |= CPM_CFCR_UPE;       /* update immediately */	REG_CPM_CFCR = cfcr;}static void jz_scale_pll(struct dpm_regs *regs){	unsigned int plcr1;	unsigned int cur_mclk, new_mclk, new_pll;	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};	int od[] = {1, 2, 2, 4};	plcr1 = REG_CPM_PLCR1;	plcr1 &= ~(regs->plcr1_mask | CPM_PLCR1_PLL1S | CPM_PLCR1_PLL1EN | CPM_PLCR1_PLL1ST_MASK);	regs->plcr1 &= ~CPM_PLCR1_PLL1EN;	plcr1 |= (regs->plcr1 | 0xff);	/* LCD and LCD pixel clocks should not be changed even if the PLL 	 * output frequency has been changed.	 */	/* Disable LCD before scaling pll */	REG_LCD_CTRL &= ~LCD_CTRL_ENA;	/* Update some DRAM parameters before changing frequency */	new_pll = JZ_EXTAL * ((plcr1>>23)+2) / ((((plcr1>>18)&0x1f)+2) * od[(plcr1>>16)&0x03]);	cur_mclk = __cpm_get_mclk();	new_mclk = new_pll / div[(REG_CPM_CFCR>>16) & 0xf];	jz_update_dram_prev(cur_mclk, new_mclk);	/* Update PLL  *///	__cpm_stop_all();	REG_CPM_PLCR1 = plcr1;	REG_CPM_PLCR1 |= CPM_PLCR1_PLL1EN;//	__cpm_start_all();	/* Update some other DRAM parameters after changing frequency */	jz_update_dram_post(cur_mclk, new_mclk);	/* Scale the LCD divisors after scaling pll */	jz_scale_lcd_divisors(regs);	/* Enable LCD */	REG_LCD_CTRL &= ~LCD_CTRL_DIS;	REG_LCD_CTRL |= LCD_CTRL_ENA;}static voidjz_init_boot_config(void){	if (!boot_config.lcd_clks_initialized) {		/* the first time to scale pll */		boot_config.lcd_clk = __cpm_get_lcdclk();		boot_config.lcdpix_clk = __cpm_get_pixclk();		boot_config.lcd_clks_initialized = 1;	}	if (!boot_config.sdram_initialized) {		/* the first time to scale frequencies */		unsigned int dmcr, rtcor;		unsigned int tras, rcd, tpc, trwl, trc;				dmcr = REG_EMC_DMCR;		rtcor = REG_EMC_RTCOR;		tras = (dmcr >> 13) & 0x7;		rcd = (dmcr >> 11) & 0x3;		tpc = (dmcr >> 8) & 0x7;		trwl = (dmcr >> 5) & 0x3;		trc = (dmcr >> 2) & 0x7;		boot_config.mclk = __cpm_get_mclk() / 1000;		boot_config.tras = tras + 4;		boot_config.rcd = rcd + 1;		boot_config.tpc = tpc + 1;		boot_config.trwl = trwl + 1;		boot_config.trc = trc * 2 + 1;		boot_config.rtcor = rtcor;		boot_config.sdram_initialized = 1;	}}static void jz_fscaler(struct dpm_regs *regs){	jz_init_boot_config();	/* the pll frequency is going up, so change dividers first */	if (regs->pll_up_flag) {		jz_scale_divisors(regs);//		jz_scale_pll(regs);	} else {//		jz_scale_pll(regs);		jz_scale_divisors(regs);	}	jz_update_clocks();}//extern void dpm_device_suspend(void);//extern void dpm_device_resume(void);static void jz_fscaler_suspend(struct dpm_regs *regs){	extern void jz_pm_suspend(void);//	dpm_device_suspend();#ifdef CONFIG_PM	jz_pm_suspend();#endif	dpm_set_os(DPM_TASK_STATE);}static void jz_fscaler_resume(struct dpm_regs *regs){	jz_fscaler(regs);//	dpm_device_resume();}/* This routine computes the "forward" frequency scaler that moves the system * from the current operating point to the new operating point.  The resulting * fscaler is applied to the registers of the new operating point.  */dpm_fscaler compute_fscaler(struct dpm_md_opt *cur, struct dpm_md_opt *new){	new->regs.pll_up_flag = (new->pll > cur->pll) ? 1 : 0;	loops_per_jiffy = new->lpj;	if (cur->cpu == 0) {		return jz_fscaler_resume;	}	if (new->cpu == 0) {		return jz_fscaler_suspend;	}	return jz_fscaler;}static unsigned long compute_lpj(unsigned long ref, u_int div, u_int mult){	unsigned long new_jiffy_l, new_jiffy_h;	/*	 * Recalculate loops_per_jiffy.  We do it this way to	 * avoid math overflow on 32-bit machines.  Maybe we	 * should make this architecture dependent?  If you have	 * a better way of doing this, please replace!	 *	 *    new = old * mult / div	 */	new_jiffy_h = ref / div;	new_jiffy_l = (ref % div) / 100;	new_jiffy_h *= mult;	new_jiffy_l = new_jiffy_l * mult / div;	return new_jiffy_h + new_jiffy_l * 100;}/* Initialize the machine-dependent operating point from a list of parameters,   which has already been installed in the pp field of the operating point.   Some of the parameters may be specified with a value of -1 to indicate a   default value. */static int check_divider(int div){	if ((div != 1) && (div != 2) && (div != 3) && (div != 4) &&	    (div != 6) && (div != 8) && (div != 12) && (div != 16) &&	    (div != 24) && (div != 32) && (div != 0)) {		return -EINVAL;	}	return 0;}