diff -burN gcc-4.1.0/config.sub gcc-psp/config.sub--- gcc-4.1.0/config.sub	2005-12-16 12:57:40.000000000 +0000+++ gcc-psp/config.sub	2006-05-07 13:27:40.000000000 +0100@@ -264,6 +264,7 @@ 	| mipsisa64sb1 | mipsisa64sb1el \ 	| mipsisa64sr71k | mipsisa64sr71kel \ 	| mipstx39 | mipstx39el \+	| mipsallegrex | mipsallegrexel \ 	| mn10200 | mn10300 \ 	| mt \ 	| msp430 \@@ -346,6 +347,7 @@ 	| mipsisa64sb1-* | mipsisa64sb1el-* \ 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \ 	| mipstx39-* | mipstx39el-* \+	| mipsallegrex-* | mipsallegrexel-* \ 	| mmix-* \ 	| mt-* \ 	| msp430-* \@@ -689,6 +691,10 @@ 		basic_machine=m68k-atari 		os=-mint 		;;+	psp)+		basic_machine=mipsallegrexel-psp+		os=-elf+		;; 	mips3*-*) 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` 		;;diff -burN gcc-4.1.0/gcc/c-incpath.c gcc-psp/gcc/c-incpath.c--- gcc-4.1.0/gcc/c-incpath.c	2005-06-25 03:02:01.000000000 +0100+++ gcc-psp/gcc/c-incpath.c	2006-05-07 13:27:40.000000000 +0100@@ -331,13 +331,18 @@   cpp_dir *p;  #if defined (HAVE_DOS_BASED_FILE_SYSTEM)-  /* Convert all backslashes to slashes.  The native CRT stat()-     function does not recognize a directory that ends in a backslash-     (unless it is a drive root dir, such "c:\").  Forward slashes,-     trailing or otherwise, cause no problems for stat().  */-  char* c;-  for (c = path; *c; c++)-    if (*c == '\\') *c = '/';+  /* Remove unnecessary trailing slashes.  On some versions of MS+     Windows, trailing  _forward_ slashes cause no problems for stat().+     On newer versions, stat() does not recognise a directory that ends+     in a '\\' or '/', unless it is a drive root dir, such as "c:/",+     where it is obligatory.  */+  int pathlen = strlen (path);+  char* end = path + pathlen - 1;+  /* Preserve the lead '/' or lead "c:/".  */+  char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1);+   +  for (; end > start && IS_DIR_SEPARATOR (*end); end--)+    *end = 0; #endif    p = xmalloc (sizeof (cpp_dir));diff -burN gcc-4.1.0/gcc/config/mips/allegrex.md gcc-psp/gcc/config/mips/allegrex.md--- gcc-4.1.0/gcc/config/mips/allegrex.md	1970-01-01 01:00:00.000000000 +0100+++ gcc-psp/gcc/config/mips/allegrex.md	2006-05-07 13:27:40.000000000 +0100@@ -0,0 +1,183 @@+;; Sony ALLEGREX instructions.+;; Copyright (C) 2005 Free Software Foundation, Inc.+;;+;; This file is part of GCC.+;;+;; GCC is free software; you can redistribute it and/or modify+;; it under the terms of the GNU General Public License as published by+;; the Free Software Foundation; either version 2, or (at your option)+;; any later version.+;;+;; GCC is distributed in the hope that it will be useful,+;; but WITHOUT ANY WARRANTY; without even the implied warranty of+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the+;; GNU General Public License for more details.+;;+;; You should have received a copy of the GNU General Public License+;; along with GCC; see the file COPYING.  If not, write to+;; the Free Software Foundation, 59 Temple Place - Suite 330,+;; Boston, MA 02111-1307, USA.++; Multiply Add and Subtract.++(define_insn "allegrex_madd"+  [(set (match_operand:SI 0 "register_operand" "+l")+      	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")+			  (match_operand:SI 2 "register_operand" "d"))+		 (match_dup 0)))+   (clobber (match_scratch:SI 3 "=h"))]+  "TARGET_ALLEGREX"+  "madd\t%1,%2"+  [(set_attr "type"	"imadd")+   (set_attr "mode"	"SI")])++(define_insn "allegrex_msub"+  [(set (match_operand:SI 0 "register_operand" "+l")+      	(minus:SI (match_dup 0)+		  (mult:SI (match_operand:SI 1 "register_operand" "d")+			   (match_operand:SI 2 "register_operand" "d"))))+   (clobber (match_scratch:SI 3 "=h"))]+  "TARGET_ALLEGREX"+  "msub\t%1,%2"+  [(set_attr "type"	"imadd")+   (set_attr "mode"	"SI")])+++; Min and max.++(define_insn "sminsi3"+  [(set (match_operand:SI 0 "register_operand" "=d")+        (smin:SI (match_operand:SI 1 "register_operand" "d")+                 (match_operand:SI 2 "register_operand" "d")))]+  "TARGET_ALLEGREX"+  "min\t%0,%1,%2"+  [(set_attr "type"	"arith")+   (set_attr "mode"	"SI")])++(define_insn "smaxsi3"+  [(set (match_operand:SI 0 "register_operand" "=d")+        (smax:SI (match_operand:SI 1 "register_operand" "d")+                 (match_operand:SI 2 "register_operand" "d")))]+  "TARGET_ALLEGREX"+  "max\t%0,%1,%2"+  [(set_attr "type"	"arith")+   (set_attr "mode"	"SI")])+++; Extended shift instructions.++(define_insn "allegrex_bitrev"+  [(set (match_operand:SI 0 "register_operand" "=d")+	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]+		   UNSPEC_BITREV))]+  "TARGET_ALLEGREX"+  "bitrev\t%0,%1"+  [(set_attr "type"	"arith")+   (set_attr "mode"	"SI")])++(define_insn "allegrex_wsbh"+  [(set (match_operand:SI 0 "register_operand" "=d")+	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]+		   UNSPEC_WSBH))]+  "TARGET_ALLEGREX"+  "wsbh\t%0,%1"+  [(set_attr "type"	"arith")+   (set_attr "mode"	"SI")])++(define_insn "allegrex_wsbw"+  [(set (match_operand:SI 0 "register_operand" "=d")+	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]+		   UNSPEC_WSBW))]+  "TARGET_ALLEGREX"+  "wsbw\t%0,%1"+  [(set_attr "type"	"arith")+   (set_attr "mode"	"SI")])+++; Count leading ones, count trailing zeros, and count trailing ones (clz is+; already defined).++(define_insn "allegrex_clo"+  [(set (match_operand:SI 0 "register_operand" "=d")+      	(unspec:SI [(match_operand:SI 1 "register_operand" "d")]+		   UNSPEC_CLO))]+  "TARGET_ALLEGREX"+  "clo\t%0,%1"+  [(set_attr "type"	"clz")+   (set_attr "mode"	"SI")])++(define_expand "ctzsi2"+  [(set (match_operand:SI 0 "register_operand")+      	(ctz:SI (match_operand:SI 1 "register_operand")))]+  "TARGET_ALLEGREX"+{+  rtx r1;++  r1 = gen_reg_rtx (SImode);+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));+  emit_insn (gen_clzsi2 (operands[0], r1));+  DONE;+})++(define_expand "allegrex_cto"+  [(set (match_operand:SI 0 "register_operand")+      	(unspec:SI [(match_operand:SI 1 "register_operand")]+		   UNSPEC_CTO))]+  "TARGET_ALLEGREX"+{+  rtx r1;++  r1 = gen_reg_rtx (SImode);+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));+  emit_insn (gen_allegrex_clo (operands[0], r1));+  DONE;+})+++; Misc.++(define_insn "allegrex_sync"+  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]+  "TARGET_ALLEGREX"+  "sync"+  [(set_attr "type"	"unknown")+   (set_attr "mode"	"none")])++(define_insn "allegrex_cache"+  [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")+		     (match_operand:SI 1 "register_operand" "d")]+		    UNSPEC_CACHE)]+  "TARGET_ALLEGREX"+  "cache\t%0,0(%1)"+  [(set_attr "type"	"unknown")+   (set_attr "mode"	"none")])+++; Floating-point builtins.++(define_insn "allegrex_ceil_w_s"+  [(set (match_operand:SI 0 "register_operand" "=f")+      	(unspec:SI [(match_operand:SF 1 "register_operand" "f")]+		   UNSPEC_CEIL_W_S))]+  "TARGET_ALLEGREX"+  "ceil.w.s\t%0,%1"+  [(set_attr "type"	"fcvt")+   (set_attr "mode"	"SF")])++(define_insn "allegrex_floor_w_s"+  [(set (match_operand:SI 0 "register_operand" "=f")+      	(unspec:SI [(match_operand:SF 1 "register_operand" "f")]+		   UNSPEC_FLOOR_W_S))]+  "TARGET_ALLEGREX"+  "floor.w.s\t%0,%1"+  [(set_attr "type"	"fcvt")+   (set_attr "mode"	"SF")])++(define_insn "allegrex_round_w_s"+  [(set (match_operand:SI 0 "register_operand" "=f")+      	(unspec:SI [(match_operand:SF 1 "register_operand" "f")]+		   UNSPEC_ROUND_W_S))]+  "TARGET_ALLEGREX"+  "round.w.s\t%0,%1"+  [(set_attr "type"	"fcvt")+   (set_attr "mode"	"SF")])diff -burN gcc-4.1.0/gcc/config/mips/mips.c gcc-psp/gcc/config/mips/mips.c--- gcc-4.1.0/gcc/config/mips/mips.c	2005-12-09 08:15:58.000000000 +0000+++ gcc-psp/gcc/config/mips/mips.c	2006-05-07 18:37:50.000000000 +0100@@ -179,6 +179,12 @@   MIPS_VOID_FTYPE_V2HI_V2HI,   MIPS_VOID_FTYPE_V4QI_V4QI, +  /* For the Sony ALLEGREX.  */+  MIPS_SI_FTYPE_QI,+  MIPS_SI_FTYPE_HI,+  MIPS_VOID_FTYPE_VOID,+  MIPS_SI_FTYPE_SF,+   /* The last type.  */   MIPS_MAX_FTYPE_MAX };@@ -220,6 +226,11 @@   /* As above, but the instruction only sets a single $fcc register.  */   MIPS_BUILTIN_CMP_SINGLE, +   /* The builtin corresponds to the ALLEGREX cache instruction.  Operand 0+      is the function code (must be less than 32) and operand 1 is the base+      address.  */+   MIPS_BUILTIN_CACHE,+   /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */   MIPS_BUILTIN_BPOSGE32 };@@ -405,6 +416,7 @@ static rtx mips_expand_builtin_compare (enum mips_builtin_type, 					enum insn_code, enum mips_fp_condition, 					rtx, tree);+static rtx mips_expand_builtin_cache (enum insn_code icode, rtx, tree); static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx); static void mips_encode_section_info (tree, rtx, int); @@ -721,6 +733,7 @@    /* MIPS II */   { "r6000", PROCESSOR_R6000, 2 },+  { "allegrex", PROCESSOR_ALLEGREX, 2 },    /* MIPS III */   { "r4000", PROCESSOR_R4000, 3 },@@ -10169,6 +10182,67 @@   BPOSGE_BUILTIN (32, MASK_DSP) }; +/* Builtin functions for the Sony ALLEGREX processor.++   These have the `__builtin_allgrex_' prefix instead of `__builtin_mips_'+   to maintain compatibility with Sony's ALLEGREX GCC port.++   Some of the builtins may seem redundant, but they are the same as the+   builtins defined in the Sony compiler.  I chose to map redundant and+   trivial builtins to the original instruction instead of creating+   duplicate patterns specifically for the ALLEGREX (as Sony does).  */++/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.+   FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields.  */+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)	\+  { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN,		\+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }++/* Same as the above, but mapped to an instruction that doesn't share the+   NAME.  NAME is the name of the builtin without the builtin prefix.  */+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS)	\+  { CODE_FOR_ ## INSN, 0, "__builtin_allegrex_" #NAME,				\+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }++/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction+   CODE_FOR_allegrex_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are+   builtin_description fields.  */+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)	\+  { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN,			\+    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }++/* Define a builtin with a specific function TYPE.  */+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS)	\+  { CODE_FOR_allegrex_ ## INSN, 0, "__builtin_allegrex_" #INSN,			\+    MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, TARGET_FLAGS }++static const struct builtin_description allegrex_bdesc[] =+{+  DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_BUILTIN(wsbw, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),++  DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),++  DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),+  SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),++  DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),+  DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),+  DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),+  DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),+  DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0)+};+ /* This helps provide a mapping from builtin function codes to bdesc    arrays.  */ @@ -10189,6 +10263,7 @@ {   { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },   { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },+  { allegrex_bdesc, ARRAY_SIZE (allegrex_bdesc), PROCESSOR_ALLEGREX },   { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX } }; @@ -10292,6 +10367,9 @@     case MIPS_BUILTIN_BPOSGE32:       return mips_expand_builtin_bposge (type, target); +    case MIPS_BUILTIN_CACHE:+      return mips_expand_builtin_cache (icode, target, arglist);+     default:       return 0;     }@@ -10310,8 +10388,8 @@   tree V4QI_type_node;   unsigned int offset; -  /* We have only builtins for -mpaired-single, -mips3d and -mdsp.  */-  if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)+  /* We have only builtins for -mpaired-single, -mips3d and -mdsp and the Sony ALLEGREX.  */+  if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP && !TARGET_ALLEGREX)     return;    if (TARGET_PAIRED_SINGLE_FLOAT)@@ -10376,6 +10454,44 @@ 				    double_type_node, double_type_node, NULL_TREE);     } +   if (TARGET_ALLEGREX)+     {+       types[MIPS_SI_FTYPE_QI]+ 	= build_function_type_list (intSI_type_node,+ 				    intQI_type_node,+ 				    NULL_TREE);+ +       types[MIPS_SI_FTYPE_HI]+ 	= build_function_type_list (intSI_type_node,+ 				    intHI_type_node,+ 				    NULL_TREE);+ +       types[MIPS_SI_FTYPE_SI]+ 	= build_function_type_list (intSI_type_node,+ 				    intSI_type_node,+ 				    NULL_TREE);+ +       types[MIPS_SI_FTYPE_SI_SI]+ 	= build_function_type_list (intSI_type_node,+ 				    intSI_type_node, intSI_type_node,+ 				    NULL_TREE);+ +       types[MIPS_VOID_FTYPE_VOID]+ 	= build_function_type_list (void_type_node, void_type_node, NULL_TREE);+ +       types[MIPS_VOID_FTYPE_SI_SI]+ 	= build_function_type_list (void_type_node,+ 				    intSI_type_node, intSI_type_node, NULL_TREE);+ +       types[MIPS_SF_FTYPE_SF]+ 	= build_function_type_list (float_type_node,+ 				    float_type_node, NULL_TREE);+