/* Definitions of target machine for GNU compiler.  MIPS version.   Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998   1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.   Contributed by A. Lichnewsky (lich@inria.inria.fr).   Changed by Michael Meissner	(meissner@osf.org).   64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and   Brendan Eich (brendan@microunity.com).This file is part of GCC.GCC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2, or (at your option)any later version.GCC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GCC; see the file COPYING.  If not, write tothe Free Software Foundation, 59 Temple Place - Suite 330,Boston, MA 02111-1307, USA.  *//* Standard GCC variables that we reference.  */extern int	target_flags;/* MIPS external variables defined in mips.c.  *//* Which processor to schedule for.  Since there is no difference between   a R2000 and R3000 in terms of the scheduler, we collapse them into   just an R3000.  The elements of the enumeration must match exactly   the cpu attribute in the mips.md machine description.  */enum processor_type {  PROCESSOR_DEFAULT,  PROCESSOR_4KC,  PROCESSOR_5KC,  PROCESSOR_20KC,  PROCESSOR_M4K,  PROCESSOR_R3000,  PROCESSOR_R3900,  PROCESSOR_R6000,  PROCESSOR_R4000,  PROCESSOR_R4100,  PROCESSOR_R4111,  PROCESSOR_R4120,  PROCESSOR_R4130,  PROCESSOR_R4300,  PROCESSOR_R4600,  PROCESSOR_R4650,  PROCESSOR_R5000,  PROCESSOR_R5400,  PROCESSOR_R5500,  PROCESSOR_R7000,  PROCESSOR_R8000,  PROCESSOR_R9000,  PROCESSOR_SB1,  PROCESSOR_SR71000,  PROCESSOR_ALLEGREX};/* Which ABI to use.  ABI_32 (original 32, or o32), ABI_N32 (n32),   ABI_64 (n64) are all defined by SGI.  ABI_O64 is o32 extended   to work on a 64 bit machine.  */#define ABI_32  0#define ABI_N32 1#define ABI_64  2#define ABI_EABI 3#define ABI_O64  4/* Information about one recognized processor.  Defined here for the   benefit of TARGET_CPU_CPP_BUILTINS.  */struct mips_cpu_info {  /* The 'canonical' name of the processor as far as GCC is concerned.     It's typically a manufacturer's prefix followed by a numerical     designation.  It should be lower case.  */  const char *name;  /* The internal processor number that most closely matches this     entry.  Several processors can have the same value, if there's no     difference between them from GCC's point of view.  */  enum processor_type cpu;  /* The ISA level that the processor implements.  */  int isa;};extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */extern const char *current_function_file; /* filename current function is in */extern int num_source_filenames;	/* current .file # */extern int mips_section_threshold;	/* # bytes of data/sdata cutoff */extern int sym_lineno;			/* sgi next label # for each stmt */extern int set_noreorder;		/* # of nested .set noreorder's  */extern int set_nomacro;			/* # of nested .set nomacro's  */extern int set_noat;			/* # of nested .set noat's  */extern int set_volatile;		/* # of nested .set volatile's  */extern int mips_branch_likely;		/* emit 'l' after br (branch likely) */extern int mips_dbx_regno[];		/* Map register # to debug register # */extern GTY(()) rtx cmp_operands[2];extern enum processor_type mips_arch;   /* which cpu to codegen for */extern enum processor_type mips_tune;   /* which cpu to schedule for */extern int mips_isa;			/* architectural level */extern int mips_abi;			/* which ABI to use */extern int mips16_hard_float;		/* mips16 without -msoft-float */extern const char *mips_arch_string;    /* for -march=<xxx> */extern const char *mips_tune_string;    /* for -mtune=<xxx> */extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */extern const char *mips_fix_vr4130_string;extern const struct mips_cpu_info mips_cpu_info_table[];extern const struct mips_cpu_info *mips_arch_info;extern const struct mips_cpu_info *mips_tune_info;/* Macros to silence warnings about numbers being signed in traditional   C and unsigned in ISO C when compiled on 32-bit hosts.  */#define BITMASK_HIGH	(((unsigned long)1) << 31)	/* 0x80000000 */#define BITMASK_UPPER16	((unsigned long)0xffff << 16)	/* 0xffff0000 */#define BITMASK_LOWER16	((unsigned long)0xffff)		/* 0x0000ffff *//* Run-time compilation parameters selecting different hardware subsets.  *//* Macros used in the machine description to test the flags.  */					/* Bits for real switches */#define MASK_INT64	   0x00000001	/* ints are 64 bits */#define MASK_LONG64	   0x00000002	/* longs are 64 bits */#define MASK_SPLIT_ADDR	   0x00000004	/* Address splitting is enabled.  */#define MASK_NO_FUSED_MADD 0x00000008   /* Don't generate floating point					   multiply-add operations.  */#define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators.  */#define MASK_MEMCPY	   0x00000020	/* call memcpy instead of inline code*/#define MASK_SOFT_FLOAT	   0x00000040	/* software floating point */#define MASK_FLOAT64	   0x00000080	/* fp registers are 64 bits */#define MASK_ABICALLS	   0x00000100	/* emit .abicalls/.cprestore/.cpload */#define MASK_XGOT	   0x00000200	/* emit big-got PIC */#define MASK_LONG_CALLS	   0x00000400	/* Always call through a register */#define MASK_64BIT	   0x00000800	/* Use 64 bit GP registers and insns */#define MASK_EMBEDDED_DATA 0x00001000	/* Reduce RAM usage, not fast code */#define MASK_BIG_ENDIAN	   0x00002000	/* Generate big endian code */#define MASK_SINGLE_FLOAT  0x00004000	/* Only single precision FPU.  */#define MASK_MAD	   0x00008000	/* Generate mad/madu as on 4650.  */#define MASK_4300_MUL_FIX  0x00010000   /* Work-around early Vr4300 CPU bug */#define MASK_MIPS16	   0x00020000	/* Generate mips16 code */#define MASK_NO_CHECK_ZERO_DIV \			   0x00040000	/* divide by zero checking */#define MASK_BRANCHLIKELY  0x00080000   /* Generate Branch Likely					   instructions.  */#define MASK_UNINIT_CONST_IN_RODATA \			   0x00100000	/* Store uninitialized					   consts in rodata */#define MASK_FIX_R4000	   0x00200000	/* Work around R4000 errata.  */#define MASK_FIX_R4400	   0x00400000	/* Work around R4400 errata.  */#define MASK_FIX_SB1	   0x00800000	/* Work around SB-1 errata.  */#define MASK_FIX_VR4120	   0x01000000   /* Work around VR4120 errata.  */#define MASK_VR4130_ALIGN  0x02000000	/* Perform VR4130 alignment opts.  */#define MASK_FP_EXCEPTIONS 0x04000000   /* FP exceptions are enabled.  */#define MASK_DIVIDE_BREAKS 0x08000000   /* Divide by zero check uses                                           break instead of trap. */#define MASK_PAIRED_SINGLE 0x10000000   /* Support paired-single FPU.  */#define MASK_MIPS3D        0x20000000   /* Support MIPS-3D instructions.  */#define MASK_SYM32	   0x40000000	/* Assume 32-bit symbol values.  */					/* Debug switches, not documented */#define MASK_DEBUG	0		/* unused */#define MASK_DEBUG_D	0		/* don't do define_split's */					/* Dummy switches used only in specs */#define MASK_MIPS_TFILE	0		/* flag for mips-tfile usage */					/* r4000 64 bit sizes */#define TARGET_INT64		((target_flags & MASK_INT64) != 0)#define TARGET_LONG64		((target_flags & MASK_LONG64) != 0)#define TARGET_FLOAT64		((target_flags & MASK_FLOAT64) != 0)#define TARGET_64BIT		((target_flags & MASK_64BIT) != 0)					/* Mips vs. GNU linker */#define TARGET_SPLIT_ADDRESSES	((target_flags & MASK_SPLIT_ADDR) != 0)					/* Debug Modes */#define TARGET_DEBUG_MODE	((target_flags & MASK_DEBUG) != 0)#define TARGET_DEBUG_D_MODE	((target_flags & MASK_DEBUG_D) != 0)					/* call memcpy instead of inline code */#define TARGET_MEMCPY		((target_flags & MASK_MEMCPY) != 0)					/* .abicalls, etc from Pyramid V.4 */#define TARGET_ABICALLS		((target_flags & MASK_ABICALLS) != 0)#define TARGET_XGOT		((target_flags & MASK_XGOT) != 0)					/* software floating point */#define TARGET_SOFT_FLOAT	((target_flags & MASK_SOFT_FLOAT) != 0)#define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)					/* always call through a register */#define TARGET_LONG_CALLS	((target_flags & MASK_LONG_CALLS) != 0)					/* for embedded systems, optimize for					   reduced RAM space instead of for					   fastest code.  */#define TARGET_EMBEDDED_DATA	((target_flags & MASK_EMBEDDED_DATA) != 0)					/* always store uninitialized const					   variables in rodata, requires					   TARGET_EMBEDDED_DATA.  */#define TARGET_UNINIT_CONST_IN_RODATA	\			((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)					/* generate big endian code.  */#define TARGET_BIG_ENDIAN	((target_flags & MASK_BIG_ENDIAN) != 0)#define TARGET_SINGLE_FLOAT	((target_flags & MASK_SINGLE_FLOAT) != 0)#define TARGET_DOUBLE_FLOAT	(! TARGET_SINGLE_FLOAT)#define TARGET_MAD		((target_flags & MASK_MAD) != 0)#define TARGET_FUSED_MADD	((target_flags & MASK_NO_FUSED_MADD) == 0)#define TARGET_4300_MUL_FIX     ((target_flags & MASK_4300_MUL_FIX) != 0)#define TARGET_CHECK_ZERO_DIV   ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)#define TARGET_DIVIDE_TRAPS     ((target_flags & MASK_DIVIDE_BREAKS) == 0)#define TARGET_BRANCHLIKELY	((target_flags & MASK_BRANCHLIKELY) != 0)#define TARGET_FIX_SB1		((target_flags & MASK_FIX_SB1) != 0)					/* Work around R4000 errata.  */#define TARGET_FIX_R4000	((target_flags & MASK_FIX_R4000) != 0)					/* Work around R4400 errata.  */#define TARGET_FIX_R4400	((target_flags & MASK_FIX_R4400) != 0)#define TARGET_FIX_VR4120	((target_flags & MASK_FIX_VR4120) != 0)#define TARGET_FIX_VR4130	(mips_fix_vr4130_string != 0)#define TARGET_VR4130_ALIGN	((target_flags & MASK_VR4130_ALIGN) != 0)#define TARGET_FP_EXCEPTIONS	((target_flags & MASK_FP_EXCEPTIONS) != 0)#define TARGET_PAIRED_SINGLE_FLOAT	\				((target_flags & MASK_PAIRED_SINGLE) != 0)#define TARGET_MIPS3D		((target_flags & MASK_MIPS3D) != 0)#define TARGET_SYM32		((target_flags & MASK_SYM32) != 0)/* True if we should use NewABI-style relocation operators for   symbolic addresses.  This is never true for mips16 code,   which has its own conventions.  */#define TARGET_EXPLICIT_RELOCS	((target_flags & MASK_EXPLICIT_RELOCS) != 0)/* True if the call patterns should be split into a jalr followed by   an instruction to restore $gp.  This is only ever true for SVR4 PIC,   in which $gp is call-clobbered.  It is only safe to split the load   from the call when every use of $gp is explicit.  */#define TARGET_SPLIT_CALLS \  (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)/* True if we can optimize sibling calls.  For simplicity, we only   handle cases in which call_insn_operand will reject invalid   sibcall addresses.  There are two cases in which this isn't true:      - TARGET_MIPS16.  call_insn_operand accepts constant addresses	but there is no direct jump instruction.  It isn't worth	using sibling calls in this case anyway; they would usually	be longer than normal calls.      - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS.  call_insn_operand	accepts global constants, but "jr $25" is the only allowed	sibcall.  */#define TARGET_SIBCALLS \  (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))/* True if .gpword or .gpdword should be used for switch tables.   Although GAS does understand .gpdword, the SGI linker mishandles   the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).   We therefore disable GP-relative switch tables for n64 on IRIX targets.  */#define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))					/* Generate mips16 code */#define TARGET_MIPS16		((target_flags & MASK_MIPS16) != 0)/* Generic ISA defines.  */#define ISA_MIPS1		    (mips_isa == 1)#define ISA_MIPS2		    (mips_isa == 2)#define ISA_MIPS3                   (mips_isa == 3)#define ISA_MIPS4		    (mips_isa == 4)#define ISA_MIPS32		    (mips_isa == 32)#define ISA_MIPS32R2		    (mips_isa == 33)#define ISA_MIPS64                  (mips_isa == 64)/* Architecture target defines.  */#define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)#define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)#define TARGET_MIPS4120             (mips_arch == PROCESSOR_R4120)#define TARGET_MIPS4130             (mips_arch == PROCESSOR_R4130)#define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)#define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)#define TARGET_MIPS7000             (mips_arch == PROCESSOR_R7000)#define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)#define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)#define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)/* Scheduling target defines.  */#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)#define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)#define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)#define TUNE_MIPS4120               (mips_tune == PROCESSOR_R4120)#define TUNE_MIPS4130               (mips_tune == PROCESSOR_R4130)#define TUNE_MIPS5000               (mips_tune == PROCESSOR_R5000)#define TUNE_MIPS5400               (mips_tune == PROCESSOR_R5400)#define TUNE_MIPS5500               (mips_tune == PROCESSOR_R5500)#define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)#define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)#define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)#define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)/* True if the pre-reload scheduler should try to create chains of   multiply-add or multiply-subtract instructions.  For example,   suppose we have:	t1 = a * b	t2 = t1 + c * d	t3 = e * f	t4 = t3 - g * h   t1 will have a higher priority than t2 and t3 will have a higher