would have been if we hadn't run out of registers.  */  bool fpr_p;  /* The number of words passed in registers, rounded up.  */  unsigned int reg_words;  /* For EABI, the offset of the first register from GP_ARG_FIRST or     FP_ARG_FIRST.  For other ABIs, the offset of the first register from     the start of the ABI's argument structure (see the CUMULATIVE_ARGS     comment for details).     The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely     on the stack.  */  unsigned int reg_offset;  /* The number of words that must be passed on the stack, rounded up.  */  unsigned int stack_words;  /* The offset from the start of the stack overflow area of the argument's     first stack word.  Only meaningful when STACK_WORDS is nonzero.  */  unsigned int stack_offset;};/* Information about an address described by mips_address_type.   ADDRESS_CONST_INT       No fields are used.   ADDRESS_REG       REG is the base register and OFFSET is the constant offset.   ADDRESS_LO_SUM       REG is the register that contains the high part of the address,       OFFSET is the symbolic address being referenced and SYMBOL_TYPE       is the type of OFFSET's symbol.   ADDRESS_SYMBOLIC       SYMBOL_TYPE is the type of symbol being referenced.  */struct mips_address_info{  enum mips_address_type type;  rtx reg;  rtx offset;  enum mips_symbol_type symbol_type;};/* One stage in a constant building sequence.  These sequences have   the form:	A = VALUE[0]	A = A CODE[1] VALUE[1]	A = A CODE[2] VALUE[2]	...   where A is an accumulator, each CODE[i] is a binary rtl operation   and each VALUE[i] is a constant integer.  */struct mips_integer_op {  enum rtx_code code;  unsigned HOST_WIDE_INT value;};/* The largest number of operations needed to load an integer constant.   The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.   When the lowest bit is clear, we can try, but reject a sequence with   an extra SLL at the end.  */#define MIPS_MAX_INTEGER_OPS 7/* Global variables for machine-dependent things.  *//* Threshold for data being put into the small data/bss area, instead   of the normal data area.  */int mips_section_threshold = -1;/* Count the number of .file directives, so that .loc is up to date.  */int num_source_filenames = 0;/* Count the number of sdb related labels are generated (to find block   start and end boundaries).  */int sdb_label_count = 0;/* Next label # for each statement for Silicon Graphics IRIS systems.  */int sym_lineno = 0;/* Linked list of all externals that are to be emitted when optimizing   for the global pointer if they haven't been declared by the end of   the program with an appropriate .comm or initialization.  */struct extern_list GTY (()){  struct extern_list *next;	/* next external */  const char *name;		/* name of the external */  int size;			/* size in bytes */};static GTY (()) struct extern_list *extern_head = 0;/* Name of the file containing the current function.  */const char *current_function_file = "";/* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */int set_noreorder;int set_noat;int set_nomacro;int set_volatile;/* The next branch instruction is a branch likely, not branch normal.  */int mips_branch_likely;/* The operands passed to the last cmpMM expander.  */rtx cmp_operands[2];/* The target cpu for code generation.  */enum processor_type mips_arch;const struct mips_cpu_info *mips_arch_info;/* The target cpu for optimization and scheduling.  */enum processor_type mips_tune;const struct mips_cpu_info *mips_tune_info;/* Which instruction set architecture to use.  */int mips_isa;/* Which ABI to use.  */int mips_abi;/* Strings to hold which cpu and instruction set architecture to use.  */const char *mips_arch_string;   /* for -march=<xxx> */const char *mips_tune_string;   /* for -mtune=<xxx> */const char *mips_isa_string;	/* for -mips{1,2,3,4} */const char *mips_abi_string;	/* for -mabi={32,n32,64,eabi} *//* Whether we are generating mips16 hard float code.  In mips16 mode   we always set TARGET_SOFT_FLOAT; this variable is nonzero if   -msoft-float was not specified by the user, which means that we   should arrange to call mips32 hard floating point code.  */int mips16_hard_float;const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;/* Holds string <X> if -mfix-vr4130<X> was passed on the command line.  */const char *mips_fix_vr4130_string;/* If TRUE, we split addresses into their high and low parts in the RTL.  */int mips_split_addresses;/* Mode used for saving/restoring general purpose registers.  */static enum machine_mode gpr_mode;/* Array giving truth value on whether or not a given hard register   can support a given mode.  */char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];/* List of all MIPS punctuation characters used by print_operand.  */char mips_print_operand_punct[256];/* Map GCC register number to debugger register number.  */int mips_dbx_regno[FIRST_PSEUDO_REGISTER];/* A copy of the original flag_delayed_branch: see override_options.  */static int mips_flag_delayed_branch;static GTY (()) int mips_output_filename_first_time = 1;/* mips_split_p[X] is true if symbols of type X can be split by   mips_split_symbol().  */static bool mips_split_p[NUM_SYMBOL_TYPES];/* mips_lo_relocs[X] is the relocation to use when a symbol of type X   appears in a LO_SUM.  It can be null if such LO_SUMs aren't valid or   if they are matched by a special .md file pattern.  */static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];/* Likewise for HIGHs.  */static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];/* Map hard register number to register class */const enum reg_class mips_regno_to_class[] ={  LEA_REGS,	LEA_REGS,	M16_NA_REGS,	M16_NA_REGS,  M16_REGS,	M16_REGS,	M16_REGS,	M16_REGS,  LEA_REGS,	LEA_REGS,	LEA_REGS,	LEA_REGS,  LEA_REGS,	LEA_REGS,	LEA_REGS,	LEA_REGS,  M16_NA_REGS,	M16_NA_REGS,	LEA_REGS,	LEA_REGS,  LEA_REGS,	LEA_REGS,	LEA_REGS,	LEA_REGS,  T_REG,	PIC_FN_ADDR_REG, LEA_REGS,	LEA_REGS,  LEA_REGS,	LEA_REGS,	LEA_REGS,	LEA_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  HI_REG,	LO_REG,		NO_REGS,	ST_REGS,  ST_REGS,	ST_REGS,	ST_REGS,	ST_REGS,  ST_REGS,	ST_REGS,	ST_REGS,	NO_REGS,  NO_REGS,	ALL_REGS,	ALL_REGS,	NO_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS};/* Map register constraint character to register class.  */enum reg_class mips_char_to_class[256];/* A table describing all the processors gcc knows about.  Names are   matched in the order listed.  The first mention of an ISA level is   taken as the canonical name for that ISA.   To ease comparison, please keep this table in the same order as   gas's mips_cpu_info_table[].  */const struct mips_cpu_info mips_cpu_info_table[] = {  /* Entries for generic ISAs */  { "mips1", PROCESSOR_R3000, 1 },  { "mips2", PROCESSOR_R6000, 2 },  { "mips3", PROCESSOR_R4000, 3 },  { "mips4", PROCESSOR_R8000, 4 },  { "mips32", PROCESSOR_4KC, 32 },  { "mips32r2", PROCESSOR_M4K, 33 },  { "mips64", PROCESSOR_5KC, 64 },  /* MIPS I */  { "r3000", PROCESSOR_R3000, 1 },  { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */  { "r3900", PROCESSOR_R3900, 1 },  /* MIPS II */  { "r6000", PROCESSOR_R6000, 2 },  { "allegrex", PROCESSOR_ALLEGREX, 2 },  /* MIPS III */  { "r4000", PROCESSOR_R4000, 3 },  { "vr4100", PROCESSOR_R4100, 3 },  { "vr4111", PROCESSOR_R4111, 3 },  { "vr4120", PROCESSOR_R4120, 3 },  { "vr4130", PROCESSOR_R4130, 3 },  { "vr4300", PROCESSOR_R4300, 3 },  { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */  { "r4600", PROCESSOR_R4600, 3 },  { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */  { "r4650", PROCESSOR_R4650, 3 },  /* MIPS IV */  { "r8000", PROCESSOR_R8000, 4 },  { "vr5000", PROCESSOR_R5000, 4 },  { "vr5400", PROCESSOR_R5400, 4 },  { "vr5500", PROCESSOR_R5500, 4 },  { "rm7000", PROCESSOR_R7000, 4 },  { "rm9000", PROCESSOR_R9000, 4 },  /* MIPS32 */  { "4kc", PROCESSOR_4KC, 32 },  { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */  /* MIPS32 Release 2 */  { "m4k", PROCESSOR_M4K, 33 },  /* MIPS64 */  { "5kc", PROCESSOR_5KC, 64 },  { "20kc", PROCESSOR_20KC, 64 },  { "sb1", PROCESSOR_SB1, 64 },  { "sr71000", PROCESSOR_SR71000, 64 },  /* End marker */  { 0, 0, 0 }};/* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT.  */#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0#endif/* Initialize the GCC target structure.  */#undef TARGET_ASM_ALIGNED_HI_OP#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"#undef TARGET_ASM_ALIGNED_SI_OP#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"#undef TARGET_ASM_ALIGNED_DI_OP#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"#undef TARGET_ASM_FUNCTION_PROLOGUE#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue#undef TARGET_ASM_FUNCTION_EPILOGUE#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue#undef TARGET_ASM_SELECT_RTX_SECTION#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section#undef TARGET_ASM_FUNCTION_RODATA_SECTION#define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section#undef TARGET_SCHED_REORDER#define TARGET_SCHED_REORDER mips_sched_reorder#undef TARGET_SCHED_VARIABLE_ISSUE#define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue#undef TARGET_SCHED_ADJUST_COST#define TARGET_SCHED_ADJUST_COST mips_adjust_cost#undef TARGET_SCHED_ISSUE_RATE#define TARGET_SCHED_ISSUE_RATE mips_issue_rate#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \  mips_multipass_dfa_lookahead#undef TARGET_FUNCTION_OK_FOR_SIBCALL#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall#undef TARGET_VALID_POINTER_MODE#define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode#undef TARGET_RTX_COSTS#define TARGET_RTX_COSTS mips_rtx_costs#undef TARGET_ADDRESS_COST#define TARGET_ADDRESS_COST mips_address_cost#undef TARGET_IN_SMALL_DATA_P#define TARGET_IN_SMALL_DATA_P mips_in_small_data_p#undef TARGET_MACHINE_DEPENDENT_REORG#define TARGET_MACHINE_DEPENDENT_REORG mips_reorg#undef TARGET_ASM_FILE_START#undef TARGET_ASM_FILE_END#define TARGET_ASM_FILE_START mips_file_start#define TARGET_ASM_FILE_END mips_file_end#undef TARGET_ASM_FILE_START_FILE_DIRECTIVE#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true#undef TARGET_INIT_LIBFUNCS#define TARGET_INIT_LIBFUNCS mips_init_libfuncs#undef TARGET_BUILD_BUILTIN_VA_LIST#define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list#undef TARGET_GIMPLIFY_VA_ARG_EXPR#define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr#undef TARGET_PROMOTE_FUNCTION_ARGS#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true#undef TARGET_PROMOTE_FUNCTION_RETURN#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true#undef TARGET_PROMOTE_PROTOTYPES#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true#undef TARGET_RETURN_IN_MEMORY#define TARGET_RETURN_IN_MEMORY mips_return_in_memory#undef TARGET_RETURN_IN_MSB#define TARGET_RETURN_IN_MSB mips_return_in_msb#undef TARGET_ASM_OUTPUT_MI_THUNK#define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true#undef TARGET_SETUP_INCOMING_VARARGS#define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs#undef TARGET_STRICT_ARGUMENT_NAMING#define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming#undef TARGET_MUST_PASS_IN_STACK#define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size#undef TARGET_PASS_BY_REFERENCE#define TARGET_PASS_BY_REFERENCE mips_pass_by_reference#undef TARGET_CALLEE_COPIES#define TARGET_CALLEE_COPIES mips_callee_copies#undef TARGET_ARG_PARTIAL_BYTES#define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes#undef TARGET_VECTOR_MODE_SUPPORTED_P#define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p#undef TARGET_SCALAR_MODE_SUPPORTED_P#define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p#undef TARGET_INIT_BUILTINS#define TARGET_INIT_BUILTINS mips_init_builtins#undef TARGET_EXPAND_BUILTIN#define TARGET_EXPAND_BUILTIN mips_expand_builtinstruct gcc_target targetm = TARGET_INITIALIZER;/* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF.  */static enum mips_symbol_typemips_classify_symbol (rtx x){  if (GET_CODE (x) == LABEL_REF)    {      if (TARGET_MIPS16)	return SYMBOL_CONSTANT_POOL;      if (TARGET_ABICALLS)	return SYMBOL_GOT_LOCAL;      return SYMBOL_GENERAL;    }  gcc_assert (GET_CODE (x) == SYMBOL_REF);  if (CONSTANT_POOL_ADDRESS_P (x))    {