;;  Mips.md	     Machine Description for MIPS based processors;;  Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,;;  1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.;;  Contributed by   A. Lichnewsky, lich@inria.inria.fr;;  Changes by       Michael Meissner, meissner@osf.org;;  64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and;;  Brendan Eich, brendan@microunity.com.;; This file is part of GCC.;; GCC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 2, or (at your option);; any later version.;; GCC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GCC; see the file COPYING.  If not, write to;; the Free Software Foundation, 59 Temple Place - Suite 330,;; Boston, MA 02111-1307, USA.(define_constants  [(UNSPEC_LOAD_DF_LOW		 0)   (UNSPEC_LOAD_DF_HIGH		 1)   (UNSPEC_STORE_DF_HIGH	 2)   (UNSPEC_GET_FNADDR		 3)   (UNSPEC_BLOCKAGE		 4)   (UNSPEC_CPRESTORE		 5)   (UNSPEC_EH_RECEIVER		 6)   (UNSPEC_EH_RETURN		 7)   (UNSPEC_CONSTTABLE_INT	 8)   (UNSPEC_CONSTTABLE_FLOAT	 9)   (UNSPEC_ALIGN		14)   (UNSPEC_HIGH			17)   (UNSPEC_LOAD_LEFT		18)   (UNSPEC_LOAD_RIGHT		19)   (UNSPEC_STORE_LEFT		20)   (UNSPEC_STORE_RIGHT		21)   (UNSPEC_LOADGP		22)   (UNSPEC_LOAD_CALL		23)   (UNSPEC_LOAD_GOT		24)   (UNSPEC_GP			25)   (UNSPEC_MFHILO		26)   (UNSPEC_ADDRESS_FIRST	100)   (FAKE_CALL_REGNO		79)   ;; For MIPS Paired-Singled Floating Point Instructions.   (UNSPEC_MOVE_TF_PS		200)   (UNSPEC_C			201)   ;; MIPS64/MIPS32R2 alnv.ps   (UNSPEC_ALNV_PS		202)   ;; MIPS-3D instructions   (UNSPEC_CABS			203)   (UNSPEC_ADDR_PS		204)   (UNSPEC_CVT_PW_PS		205)   (UNSPEC_CVT_PS_PW		206)   (UNSPEC_MULR_PS		207)   (UNSPEC_RSQRT1		208)   (UNSPEC_RSQRT2		209)   (UNSPEC_RECIP1		210)   (UNSPEC_RECIP2		211)  ])(include "predicates.md");; ....................;;;;	Attributes;;;; ....................(define_attr "got" "unset,xgot_high,load"  (const_string "unset"));; For jal instructions, this attribute is DIRECT when the target address;; is symbolic and INDIRECT when it is a register.(define_attr "jal" "unset,direct,indirect"  (const_string "unset"));; This attribute is YES if the instruction is a jal macro (not a;; real jal instruction).;;;; jal is always a macro in SVR4 PIC since it includes an instruction to;; restore $gp.  Direct jals are also macros in NewABI PIC since they;; load the target address into $25.(define_attr "jal_macro" "no,yes"  (cond [(eq_attr "jal" "direct")	 (symbol_ref "TARGET_ABICALLS != 0")	 (eq_attr "jal" "indirect")	 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]	(const_string "no")));; Classification of each insn.;; branch	conditional branch;; jump		unconditional jump;; call		unconditional call;; load		load instruction(s);; fpload	floating point load;; fpidxload    floating point indexed load;; store	store instruction(s);; fpstore	floating point store;; fpidxstore	floating point indexed store;; prefetch	memory prefetch (register + offset);; prefetchx	memory indexed prefetch (register + register);; condmove	conditional moves;; xfer		transfer to/from coprocessor;; mthilo	transfer to hi/lo registers;; mfhilo	transfer from hi/lo registers;; const	load constant;; arith	integer arithmetic and logical instructions;; shift	integer shift instructions;; slt		set less than instructions;; clz		the clz and clo instructions;; trap		trap if instructions;; imul		integer multiply;; imadd	integer multiply-add;; idiv		integer divide;; fmove	floating point register move;; fadd		floating point add/subtract;; fmul		floating point multiply;; fmadd	floating point multiply-add;; fdiv		floating point divide;; frdiv	floating point reciprocal divide;; frdiv1	floating point reciprocal divide step 1;; frdiv2	floating point reciprocal divide step 2;; fabs		floating point absolute value;; fneg		floating point negation;; fcmp		floating point compare;; fcvt		floating point convert;; fsqrt	floating point square root;; frsqrt       floating point reciprocal square root;; frsqrt1      floating point reciprocal square root step1;; frsqrt2      floating point reciprocal square root step2;; multi	multiword sequence (or user asm statements);; nop		no operation(define_attr "type"  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"  (cond [(eq_attr "jal" "!unset") (const_string "call")	 (eq_attr "got" "load") (const_string "load")]	(const_string "unknown")));; Main data type used by the insn(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"  (const_string "unknown"));; Is this an extended instruction in mips16 mode?(define_attr "extended_mips16" "no,yes"  (const_string "no"));; Length of instruction in bytes.(define_attr "length" ""   (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].	  ;; If a branch is outside this range, we have a choice of two	  ;; sequences.  For PIC, an out-of-range branch like:	  ;;	  ;;	bne	r1,r2,target	  ;;	dslot	  ;;	  ;; becomes the equivalent of:	  ;;	  ;;	beq	r1,r2,1f	  ;;	dslot	  ;;	la	$at,target	  ;;	jr	$at	  ;;	nop	  ;; 1:	  ;;	  ;; where the load address can be up to three instructions long	  ;; (lw, nop, addiu).	  ;;	  ;; The non-PIC case is similar except that we use a direct	  ;; jump instead of an la/jr pair.  Since the target of this	  ;; jump is an absolute 28-bit bit address (the other bits	  ;; coming from the address of the delay slot) this form cannot	  ;; cross a 256MB boundary.  We could provide the option of	  ;; using la/jr in this case too, but we do not do so at	  ;; present.	  ;;	  ;; Note that this value does not account for the delay slot	  ;; instruction, whose length is added separately.  If the RTL	  ;; pattern has no explicit delay slot, mips_adjust_insn_length	  ;; will add the length of the implicit nop.  The values for	  ;; forward and backward branches will be different as well.	  (eq_attr "type" "branch")	  (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))                      (le (minus (pc) (match_dup 1)) (const_int 131068)))                  (const_int 4)		 (ne (symbol_ref "flag_pic") (const_int 0))		 (const_int 24)		 ] (const_int 12))	  (eq_attr "got" "load")	  (const_int 4)	  (eq_attr "got" "xgot_high")	  (const_int 8)	  (eq_attr "type" "const")	  (symbol_ref "mips_const_insns (operands[1]) * 4")	  (eq_attr "type" "load,fpload")	  (symbol_ref "mips_fetch_insns (operands[1]) * 4")	  (eq_attr "type" "store,fpstore")	  (symbol_ref "mips_fetch_insns (operands[0]) * 4")	  ;; In the worst case, a call macro will take 8 instructions:	  ;;	  ;;	 lui $25,%call_hi(FOO)	  ;;	 addu $25,$25,$28	  ;;     lw $25,%call_lo(FOO)($25)	  ;;	 nop	  ;;	 jalr $25	  ;;	 nop	  ;;	 lw $gp,X($sp)	  ;;	 nop	  (eq_attr "jal_macro" "yes")	  (const_int 32)	  (and (eq_attr "extended_mips16" "yes")	       (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))	  (const_int 8)	  ;; Various VR4120 errata require a nop to be inserted after a macc	  ;; instruction.  The assembler does this for us, so account for	  ;; the worst-case length here.	  (and (eq_attr "type" "imadd")	       (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))	  (const_int 8)	  ;; VR4120 errata MD(4): if there are consecutive dmult instructions,	  ;; the result of the second one is missed.  The assembler should work	  ;; around this by inserting a nop after the first dmult.	  (and (eq_attr "type" "imul")	       (and (eq_attr "mode" "DI")		    (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))	  (const_int 8)	  (eq_attr "type" "idiv")	  (symbol_ref "mips_idiv_insns () * 4")	  ] (const_int 4)));; Attribute describing the processor.  This attribute must match exactly;; with the processor_type enumeration in mips.h.(define_attr "cpu"  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"  (const (symbol_ref "mips_tune")));; The type of hardware hazard associated with this instruction.;; DELAY means that the next instruction cannot read the result;; of this one.  HILO means that the next two instructions cannot;; write to HI or LO.(define_attr "hazard" "none,delay,hilo"  (cond [(and (eq_attr "type" "load,fpload,fpidxload")	      (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))	 (const_string "delay")	 (and (eq_attr "type" "xfer")	      (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))	 (const_string "delay")	 (and (eq_attr "type" "fcmp")	      (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))	 (const_string "delay")	 ;; The r4000 multiplication patterns include an mflo instruction.	 (and (eq_attr "type" "imul")	      (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))	 (const_string "hilo")	 (and (eq_attr "type" "mfhilo")	      (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))	 (const_string "hilo")]	(const_string "none")));; Is it a single instruction?(define_attr "single_insn" "no,yes"  (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"));; Can the instruction be put into a delay slot?(define_attr "can_delay" "no,yes"  (if_then_else (and (eq_attr "type" "!branch,call,jump")		     (and (eq_attr "hazard" "none")			  (eq_attr "single_insn" "yes")))		(const_string "yes")		(const_string "no")));; Attribute defining whether or not we can use the branch-likely instructions(define_attr "branch_likely" "no,yes"  (const   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))		 (const_string "yes")		 (const_string "no"))));; True if an instruction might assign to hi or lo when reloaded.;; This is used by the TUNE_MACC_CHAINS code.(define_attr "may_clobber_hilo" "no,yes"  (if_then_else (eq_attr "type" "imul,imadd,idiv,mthilo")		(const_string "yes")		(const_string "no")));; Describe a user's asm statement.(define_asm_attributes  [(set_attr "type" "multi")   (set_attr "can_delay" "no")]);; This mode macro allows 32-bit and 64-bit GPR patterns to be generated;; from the same template.(define_mode_macro GPR [SI (DI "TARGET_64BIT")]);; This mode macro allows :P to be used for patterns that operate on;; pointer-sized quantities.  Exactly one of the two alternatives will match.(define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]);; This mode macro allows :MOVECC to be used anywhere that a;; conditional-move-type condition is needed.(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")]);; This mode macro allows the QI and HI extension patterns to be defined from;; the same template.(define_mode_macro SHORT [QI HI]);; This mode macro allows :ANYF to be used wherever a scalar or vector;; floating-point mode is allowed.(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")			 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")			 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")]);; Like ANYF, but only applies to scalar modes.(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")			    (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")]);; In GPR templates, a string like "<d>subu" will expand to "subu" in the;; 32-bit version and "dsubu" in the 64-bit version.(define_mode_attr d [(SI "") (DI "d")]);; This attribute gives the length suffix for a sign- or zero-extension;; instruction.(define_mode_attr size [(QI "b") (HI "h")]);; This attributes gives the mode mask of a SHORT.(define_mode_attr mask [(QI "0x00ff") (HI "0xffff")]);; Mode attributes for GPR loads and stores.(define_mode_attr load [(SI "lw") (DI "ld")])(define_mode_attr store [(SI "sw") (DI "sd")]);; Similarly for MIPS IV indexed FPR loads and stores.(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])(define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")]);; The unextended ranges of the MIPS16 addiu and daddiu instructions;; are different.  Some forms of unextended addiu have an 8-bit immediate;; field but the equivalent daddiu has only a 5-bit field.(define_mode_attr si8_di5 [(SI "8") (DI "5")]);; This attribute gives the best constraint to use for registers of;; a given mode.(define_mode_attr reg [(SI "d") (DI "d") (CC "z")]);; This attribute gives the format suffix for floating-point operations.(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")]);; This attribute gives the upper-case mode name for one unit of a;; floating-point mode.(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")]);; This attribute works around the early SB-1 rev2 core "F2" erratum:;;;; In certain cases, div.s and div.ps may have a rounding error;; and/or wrong inexact flag.;;;; Therefore, we only allow div.s if not working around SB-1 rev2;; errata or if a slight loss of precision is OK.(define_mode_attr divide_condition  [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")   (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")]); This attribute gives the condition for which sqrt instructions exist.(define_mode_attr sqrt_condition  [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")]); This attribute gives the condition for which recip and rsqrt instructions; exist.(define_mode_attr recip_condition  [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")]);; This code macro allows all branch instructions to be generated from;; a single define_expand template.(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt			     eq ne gt ge lt le gtu geu ltu leu]);; This code macro allows signed and unsigned widening multiplications;; to use the same template.(define_code_macro any_extend [sign_extend zero_extend])