;; This code macro allows the three shift instructions to be generated;; from the same template.(define_code_macro any_shift [ashift ashiftrt lshiftrt]);; This code macro allows all native floating-point comparisons to be;; generated from the same template.(define_code_macro fcond [unordered uneq unlt unle eq lt le]);; <u> expands to an empty string when doing a signed operation and;; "u" when doing an unsigned operation.(define_code_attr u [(sign_extend "") (zero_extend "u")]);; <su> is like <u>, but the signed form expands to "s" rather than "".(define_code_attr su [(sign_extend "s") (zero_extend "u")]);; <optab> expands to the name of the optab for a particular code.(define_code_attr optab [(ashift "ashl")			 (ashiftrt "ashr")			 (lshiftrt "lshr")]);; <insn> expands to the name of the insn that implements a particular code.(define_code_attr insn [(ashift "sll")			(ashiftrt "sra")			(lshiftrt "srl")]);; <fcond> is the c.cond.fmt condition associated with a particular code.(define_code_attr fcond [(unordered "un")			 (uneq "ueq")			 (unlt "ult")			 (unle "ule")			 (eq "eq")			 (lt "lt")			 (le "le")]);; .........................;;;;	Branch, call and jump delay slots;;;; .........................(define_delay (and (eq_attr "type" "branch")		   (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))  [(eq_attr "can_delay" "yes")   (nil)   (and (eq_attr "branch_likely" "yes")	(eq_attr "can_delay" "yes"))])(define_delay (eq_attr "type" "jump")  [(eq_attr "can_delay" "yes")   (nil)   (nil)])(define_delay (and (eq_attr "type" "call")		   (eq_attr "jal_macro" "no"))  [(eq_attr "can_delay" "yes")   (nil)   (nil)]);; Pipeline descriptions.;;;; generic.md provides a fallback for processors without a specific;; pipeline description.  It is derived from the old define_function_unit;; version and uses the "alu" and "imuldiv" units declared below.;;;; Some of the processor-specific files are also derived from old;; define_function_unit descriptions and simply override the parts of;; generic.md that don't apply.  The other processor-specific files;; are self-contained.(define_automaton "alu,imuldiv")(define_cpu_unit "alu" "alu")(define_cpu_unit "imuldiv" "imuldiv")(include "3000.md")(include "4000.md")(include "4100.md")(include "4130.md")(include "4300.md")(include "4600.md")(include "5000.md")(include "5400.md")(include "5500.md")(include "6000.md")(include "7000.md")(include "9000.md")(include "sb1.md")(include "sr71k.md")(include "generic.md");;;;  ....................;;;;	CONDITIONAL TRAPS;;;;  ....................;;(define_insn "trap"  [(trap_if (const_int 1) (const_int 0))]  ""{  if (ISA_HAS_COND_TRAP)    return "teq\t$0,$0";  else if (TARGET_MIPS16)    return "break 0";  else    return "break";}  [(set_attr "type" "trap")])(define_expand "conditional_trap"  [(trap_if (match_operator 0 "comparison_operator"			    [(match_dup 2) (match_dup 3)])	    (match_operand 1 "const_int_operand"))]  "ISA_HAS_COND_TRAP"{  if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT      && operands[1] == const0_rtx)    {      mips_gen_conditional_trap (operands);      DONE;    }  else    FAIL;})(define_insn "*conditional_trap<mode>"  [(trap_if (match_operator:GPR 0 "trap_comparison_operator"				[(match_operand:GPR 1 "reg_or_0_operand" "dJ")				 (match_operand:GPR 2 "arith_operand" "dI")])	    (const_int 0))]  "ISA_HAS_COND_TRAP"  "t%C0\t%z1,%2"  [(set_attr "type" "trap")]);;;;  ....................;;;;	ADDITION;;;;  ....................;;(define_insn "add<mode>3"  [(set (match_operand:ANYF 0 "register_operand" "=f")	(plus:ANYF (match_operand:ANYF 1 "register_operand" "f")		   (match_operand:ANYF 2 "register_operand" "f")))]  ""  "add.<fmt>\t%0,%1,%2"  [(set_attr "type" "fadd")   (set_attr "mode" "<UNITMODE>")])(define_expand "add<mode>3"  [(set (match_operand:GPR 0 "register_operand")	(plus:GPR (match_operand:GPR 1 "register_operand")		  (match_operand:GPR 2 "arith_operand")))]  "")(define_insn "*add<mode>3"  [(set (match_operand:GPR 0 "register_operand" "=d,d")	(plus:GPR (match_operand:GPR 1 "register_operand" "d,d")		  (match_operand:GPR 2 "arith_operand" "d,Q")))]  "!TARGET_MIPS16"  "@    <d>addu\t%0,%1,%2    <d>addiu\t%0,%1,%2"  [(set_attr "type" "arith")   (set_attr "mode" "<MODE>")]);; We need to recognize MIPS16 stack pointer additions explicitly, since;; we don't have a constraint for $sp.  These insns will be generated by;; the save_restore_insns functions.(define_insn "*add<mode>3_sp1"  [(set (reg:GPR 29)	(plus:GPR (reg:GPR 29)		  (match_operand:GPR 0 "const_arith_operand" "")))]  "TARGET_MIPS16"  "<d>addiu\t%$,%$,%0"  [(set_attr "type" "arith")   (set_attr "mode" "<MODE>")   (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")				      (const_int 4)				      (const_int 8)))])(define_insn "*add<mode>3_sp2"  [(set (match_operand:GPR 0 "register_operand" "=d")	(plus:GPR (reg:GPR 29)		  (match_operand:GPR 1 "const_arith_operand" "")))]  "TARGET_MIPS16"  "<d>addiu\t%0,%$,%1"  [(set_attr "type" "arith")   (set_attr "mode" "<MODE>")   (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")				      (const_int 4)				      (const_int 8)))])(define_insn "*add<mode>3_mips16"  [(set (match_operand:GPR 0 "register_operand" "=d,d,d")	(plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")		  (match_operand:GPR 2 "arith_operand" "Q,O,d")))]  "TARGET_MIPS16"  "@    <d>addiu\t%0,%2    <d>addiu\t%0,%1,%2    <d>addu\t%0,%1,%2"  [(set_attr "type" "arith")   (set_attr "mode" "<MODE>")   (set_attr_alternative "length"		[(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")			       (const_int 4)			       (const_int 8))		 (if_then_else (match_operand 2 "m16_simm4_1")			       (const_int 4)			       (const_int 8))		 (const_int 4)])]);; On the mips16, we can sometimes split an add of a constant which is;; a 4 byte instruction into two adds which are both 2 byte;; instructions.  There are two cases: one where we are adding a;; constant plus a register to another register, and one where we are;; simply adding a constant to a register.(define_split  [(set (match_operand:SI 0 "register_operand")	(plus:SI (match_dup 0)		 (match_operand:SI 1 "const_int_operand")))]  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE   && REG_P (operands[0])   && M16_REG_P (REGNO (operands[0]))   && GET_CODE (operands[1]) == CONST_INT   && ((INTVAL (operands[1]) > 0x7f	&& INTVAL (operands[1]) <= 0x7f + 0x7f)       || (INTVAL (operands[1]) < - 0x80	   && INTVAL (operands[1]) >= - 0x80 - 0x80))"  [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]{  HOST_WIDE_INT val = INTVAL (operands[1]);  if (val >= 0)    {      operands[1] = GEN_INT (0x7f);      operands[2] = GEN_INT (val - 0x7f);    }  else    {      operands[1] = GEN_INT (- 0x80);      operands[2] = GEN_INT (val + 0x80);    }})(define_split  [(set (match_operand:SI 0 "register_operand")	(plus:SI (match_operand:SI 1 "register_operand")		 (match_operand:SI 2 "const_int_operand")))]  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE   && REG_P (operands[0])   && M16_REG_P (REGNO (operands[0]))   && REG_P (operands[1])   && M16_REG_P (REGNO (operands[1]))   && REGNO (operands[0]) != REGNO (operands[1])   && GET_CODE (operands[2]) == CONST_INT   && ((INTVAL (operands[2]) > 0x7	&& INTVAL (operands[2]) <= 0x7 + 0x7f)       || (INTVAL (operands[2]) < - 0x8	   && INTVAL (operands[2]) >= - 0x8 - 0x80))"  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]{  HOST_WIDE_INT val = INTVAL (operands[2]);  if (val >= 0)    {      operands[2] = GEN_INT (0x7);      operands[3] = GEN_INT (val - 0x7);    }  else    {      operands[2] = GEN_INT (- 0x8);      operands[3] = GEN_INT (val + 0x8);    }})(define_split  [(set (match_operand:DI 0 "register_operand")	(plus:DI (match_dup 0)		 (match_operand:DI 1 "const_int_operand")))]  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE   && REG_P (operands[0])   && M16_REG_P (REGNO (operands[0]))   && GET_CODE (operands[1]) == CONST_INT   && ((INTVAL (operands[1]) > 0xf	&& INTVAL (operands[1]) <= 0xf + 0xf)       || (INTVAL (operands[1]) < - 0x10	   && INTVAL (operands[1]) >= - 0x10 - 0x10))"  [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]{  HOST_WIDE_INT val = INTVAL (operands[1]);  if (val >= 0)    {      operands[1] = GEN_INT (0xf);      operands[2] = GEN_INT (val - 0xf);    }  else    {      operands[1] = GEN_INT (- 0x10);      operands[2] = GEN_INT (val + 0x10);    }})(define_split  [(set (match_operand:DI 0 "register_operand")	(plus:DI (match_operand:DI 1 "register_operand")		 (match_operand:DI 2 "const_int_operand")))]  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE   && REG_P (operands[0])   && M16_REG_P (REGNO (operands[0]))   && REG_P (operands[1])   && M16_REG_P (REGNO (operands[1]))   && REGNO (operands[0]) != REGNO (operands[1])   && GET_CODE (operands[2]) == CONST_INT   && ((INTVAL (operands[2]) > 0x7	&& INTVAL (operands[2]) <= 0x7 + 0xf)       || (INTVAL (operands[2]) < - 0x8	   && INTVAL (operands[2]) >= - 0x8 - 0x10))"  [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))   (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]{  HOST_WIDE_INT val = INTVAL (operands[2]);  if (val >= 0)    {      operands[2] = GEN_INT (0x7);      operands[3] = GEN_INT (val - 0x7);    }  else    {      operands[2] = GEN_INT (- 0x8);      operands[3] = GEN_INT (val + 0x8);    }})(define_insn "*addsi3_extended"  [(set (match_operand:DI 0 "register_operand" "=d,d")	(sign_extend:DI	     (plus:SI (match_operand:SI 1 "register_operand" "d,d")		      (match_operand:SI 2 "arith_operand" "d,Q"))))]  "TARGET_64BIT && !TARGET_MIPS16"  "@    addu\t%0,%1,%2    addiu\t%0,%1,%2"  [(set_attr "type" "arith")   (set_attr "mode" "SI")]);; Split this insn so that the addiu splitters can have a crack at it.;; Use a conservative length estimate until the split.(define_insn_and_split "*addsi3_extended_mips16"  [(set (match_operand:DI 0 "register_operand" "=d,d,d")	(sign_extend:DI	     (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")		      (match_operand:SI 2 "arith_operand" "Q,O,d"))))]  "TARGET_64BIT && TARGET_MIPS16"  "#"  "&& reload_completed"  [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]  { operands[3] = gen_lowpart (SImode, operands[0]); }  [(set_attr "type" "arith")   (set_attr "mode" "SI")   (set_attr "extended_mips16" "yes")]);;;;  ....................;;;;	SUBTRACTION;;;;  ....................;;(define_insn "sub<mode>3"  [(set (match_operand:ANYF 0 "register_operand" "=f")	(minus:ANYF (match_operand:ANYF 1 "register_operand" "f")		    (match_operand:ANYF 2 "register_operand" "f")))]  ""  "sub.<fmt>\t%0,%1,%2"  [(set_attr "type" "fadd")   (set_attr "mode" "<UNITMODE>")])(define_insn "sub<mode>3"  [(set (match_operand:GPR 0 "register_operand" "=d")	(minus:GPR (match_operand:GPR 1 "register_operand" "d")		   (match_operand:GPR 2 "register_operand" "d")))]  ""  "<d>subu\t%0,%1,%2"  [(set_attr "type" "arith")   (set_attr "mode" "<MODE>")])(define_insn "*subsi3_extended"  [(set (match_operand:DI 0 "register_operand" "=d")	(sign_extend:DI