?? zd1205.h
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#define Wep_Protect 0x063C
#define RX_THRESHOLD 0x0640
#define TX_PE_CTRL 0x0644
#if defined(AMAC)
#define AfterPNP 0x0648
#endif
#if defined(OFDM)
#define AckTime80211 0x0658
#endif
#define Rx_OFFSET 0x065c
#define PHYDelay 0x066C
#define BCNFIFO 0x0670
#define SnifferOn 0x0674
#define EncryptionType 0x0678
#define RetryMAX 0x067C
#define CtlReg1 0x0680 //Bit0: IBSS mode
//Bit1: PwrMgt mode
//Bit2-4 : Highest basic Rate
//Bit5: Lock bit
//Bit6: PLCP weight select
//Bit7: PLCP switch
#define DeviceState 0x0684
#define UnderrunCnt 0x0688
#define Rx_Filter 0x068c
#define Ack_Timeout_Ext 0x0690
#define BCN_FIFO_Semaphore 0x0694
#define IFS_Value 0x0698
#define RX_TIME_OUT 0x069C
#define TotalRxFrm 0x06A0
#define CRC32Cnt 0x06A4
#define CRC16Cnt 0x06A8
#define DecrypErr_UNI 0x06AC
#define RxFIFOOverrun 0x06B0
#define DecrypErr_Mul 0x06BC
#define NAV_CNT 0x06C4
#define NAV_CCA 0x06C8
#define RetryCnt 0x06CC
#define ReadTcbAddress 0x06E8
#define ReadRfdAddress 0x06EC
#define CWmin_CWmax 0x06F0
#define TotalTxFrm 0x06F4
#define RX_OFFSET_BYTE 0x06F8
#define CAM_MODE 0x0700
#define CAM_ROLL_TB_LOW 0x0704
#define CAM_ROLL_TB_HIGH 0x0708
#define CAM_ADDRESS 0x070C
#define CAM_DATA 0x0710
#define DECRY_ERR_FLG_LOW 0x0714
#define DECRY_ERR_FLG_HIGH 0x0718
#define WEPKey0 0x0720
#define WEPKey1 0x0724
#define WEPKey2 0x0728
#define WEPKey3 0x072C
#define CAM_DEBUG 0x0728
#define CAM_STATUS 0x072c
#define WEPKey4 0x0730
#define WEPKey5 0x0734
#define WEPKey6 0x0738
#define WEPKey7 0x073C
#define WEPKey8 0x0740
#define WEPKey9 0x0744
#define WEPKey10 0x0748
#define WEPKey11 0x074C
#define WEPKey12 0x0750
#define WEPKey13 0x0754
#define WEPKey14 0x0758
#define WEPKey15 0x075c
#define TKIP_MODE 0x0760
#define Dbg_FIFO_Rd 0x0800
#define Dbg_Select 0x0804
#define FIFO_Length 0x0808
//#define RF_Mode 0x080C
#define RSSI_MGC 0x0810
#define PON 0x0818
#define Rx_ON 0x081C
#define Tx_ON 0x0820
#define CHIP_EN 0x0824
#define LO_SW 0x0828
#define TxRx_SW 0x082C
#define S_MD 0x0830
#define USB_DEBUG_PORT 0x0888
// EEPROM Memmory Map Region
#define E2P_SUBID 0x0900
#define E2P_POD 0x0904
#define E2P_MACADDR_P1 0x0908
#define E2P_MACADDR_P2 0x090C
#ifndef HOST_IF_USB
#define E2P_PWR_CAL_VALUE 0x0910
#define E2P_PWR_INT_VALUE 0x0920
#define E2P_ALLOWED_CHANNEL 0x0930
#define E2P_PHY_REG 0x0934
#define E2P_REGION_CODE 0x0960
#define E2P_FEATURE_BITMAP 0x0964
#endif
//-------------------------------------------------------------------------
// Command Block (CB) Field Definitions
//-------------------------------------------------------------------------
//- RFD Command Bits
#define RFD_EL_BIT BIT_0 // RFD EL Bit
//- CB Command Word
#define CB_S_BIT 0x1 // CB Suspend Bit
//- CB Status Word
#define CB_STATUS_COMPLETE 0x1234 // CB Complete Bit
#define RFD_STATUS_COMPLETE 0x1234 //0x34120000 // RFD Complete Bit
/**************************************************************************
** MAC Register Bit Definitions
***************************************************************************
*/
// Interrupt STATUS
#define TX_COMPLETE BIT_0
#define RX_COMPLETE BIT_1
#define RETRY_FAIL BIT_2
#define WAKE_UP BIT_3
#define DTIM_NOTIFY BIT_5
#define CFG_NEXT_BCN BIT_6
#define BUS_ABORT BIT_7
#define TX_FIFO_READY BIT_8
#define UART_INT BIT_9
#define TX_COMPLETE_EN BIT_16
#define RX_COMPLETE_EN BIT_17
#define RETRY_FAIL_EN BIT_18
#define WAKE_UP_EN BIT_19
#define DTIM_NOTIFY_EN BIT_21
#define CFG_NEXT_BCN_EN BIT_22
#define BUS_ABORT_EN BIT_23
#define TX_FIFO_READY_EN BIT_24
#define UART_INT_EN BIT_25
#define FILTER_BEACON 0xFEFF //mask bit 8
#define UN_FILTER_PS_POLL 0x0400
#define RX_LEN_THRESHOLD 0x640 //1600
#define DBG_MSG_SHOW 0x1
#define DBG_MSG_HIDE 0x0
#define RFD_POINTER(skb, macp) ((zd1205_RFD_t *) (((unsigned char *)((skb)->data))-((macp)->rfd_size)))
#define SKB_RFD_STATUS(skb, macp) ((RFD_POINTER((skb),(macp)))->CbStatus)
/**************************************************************************
** Descriptor Data Structure
***************************************************************************/
struct driver_stats {
struct net_device_stats net_stats;
unsigned long tx_late_col;
unsigned long tx_ok_defrd;
unsigned long tx_one_retry;
unsigned long tx_mt_one_retry;
unsigned long rcv_cdt_frames;
unsigned long xmt_fc_pkts;
unsigned long rcv_fc_pkts;
unsigned long rcv_fc_unsupported;
unsigned long xmt_tco_pkts;
unsigned long rcv_tco_pkts;
unsigned long rx_intr_pkts;
};
//-------------------------------------------------------------------------
// Transmit Command Block (TxCB)
//-------------------------------------------------------------------------
typedef struct zd1205_HwTCB_s {
u32 CbStatus; // Bolck status
u32 CbCommand; // Block command
u32 NextCbPhyAddrLowPart; // Next TCB address(low part)
u32 NextCbPhyAddrHighPart; // Next TCB address(high part)
u32 TxCbFirstTbdAddrLowPart; // First TBD address(low part)
u32 TxCbFirstTbdAddrHighPart; // First TBD address(high part)
u32 TxCbTbdNumber; // Number of TBDs for this TCB
} zd1205_HwTCB_t;
//-------------------------------------------------------------------------
// Transmit Buffer Descriptor (TBD)
//-------------------------------------------------------------------------
typedef struct zd1205_TBD_s {
u32 TbdBufferAddrLowPart; // Physical Transmit Buffer Address
u32 TbdBufferAddrHighPart; // Physical Transmit Buffer Address
u32 TbdCount; // Data length
#ifdef HOST_IF_USB
u32 PrvFragLen;
#endif
} zd1205_TBD_t;
//-------------------------------------------------------------------------
// Receive Frame Descriptor (RFD)
//-------------------------------------------------------------------------
typedef struct zd1205_RFD_s {
u32 CbStatus; // Bolck status
u32 ActualCount; // Rx buffer length
u32 CbCommand; // Block command
u32 MaxSize; //
u32 NextCbPhyAddrLowPart; // Next RFD address(low part)
u32 NextCbPhyAddrHighPart; // Next RFD address(high part)
u8 RxBuffer[MAX_WLAN_SIZE]; // Rx buffer
u32 Pad[2]; // Pad to 16 bytes alignment - easy view for debug
} __attribute__ ((__packed__)) zd1205_RFD_t;
typedef struct zd1205_Ctrl_Set_s {
u8 CtrlSetting[40];
} zd1205_Ctrl_Set_t;
typedef struct zd1205_Header_s {
u8 MacHeader[36];
} zd1205_Header_t;
//-------------------------------------------------------------------------
// ZD1205SwTcb -- Software Transmit Control Block. This structure contains
// all of the variables that are related to a specific Transmit Control
// block (TCB)
//-------------------------------------------------------------------------
typedef struct zd1205_SwTcb_s {
// Link to the next SwTcb in the list
struct zd1205_SwTcb_s *next;
struct sk_buff *skb;
// physical and virtual pointers to the hardware TCB
zd1205_HwTCB_t *pTcb;
dma_addr_t TcbPhys;
// Physical and virtual pointers to the TBD array for this TCB
zd1205_TBD_t *pFirstTbd;
dma_addr_t FirstTbdPhys;
zd1205_Ctrl_Set_t *pHwCtrlPtr;
dma_addr_t HwCtrlPhys;
zd1205_Header_t *pHwHeaderPtr;
dma_addr_t HwHeaderPhys;
u32 TcbCount;
u8 LastFrag;
u8 MsgID;
u8 FrameType;
u8 Rate;
u16 aid;
u8 bIntraBss;
#if ZDCONF_LP_SUPPORT == 1
U32 TotalLen;
// U8 PackInfo[18];
U8 Padding[3]; //Used as Padding Content for A-MSDU
U8 HdrInfo[8][16];
void *LP_bucket;
#endif
//u8 encryType;
#ifdef HOST_IF_USB
u8 bHasCompleteBeforeSend;
u8 bHasBeenDelayedBefore;
#endif
u8 CalMIC[MIC_LNG+1];
u8 MIC_Start;
u8 MIC_Len;
u32 LengthDiff;
} zd1205_SwTcb_t;
typedef struct SwTcbQ_s
{
zd1205_SwTcb_t *first; /* first zd1205_SwTcb_t in Q */
zd1205_SwTcb_t *last; /* last zd1205_SwTcb_t in Q */
u16 count; /* number of zd1205_SwTcb_t in Q */
} zd1205_SwTcbQ_t;
//- Wireless 24-byte Header
typedef struct wla_Header_s {
u8 FrameCtrl[2];
u8 Duration[2];
u8 DA[6];
u8 BSSID[6];
u8 SA[6];
u8 SeqCtrl[2];
} wla_Header_t;
struct hostap_ieee80211_hdr {
u16 frame_control;
u16 duration_id;
u8 addr1[6];
u8 addr2[6];
u8 addr3[6];
u16 seq_ctrl;
u8 addr4[6];
} __attribute__ ((packed));
//from station
typedef struct plcp_wla_Header_s {
u8 PlcpHdr[PLCP_HEADER]; //Oh! shit!!!
u8 FrameCtrl[2];
u8 Duration[2];
u8 Address1[6];
u8 Address2[6];
u8 Address3[6];
u8 SeqCtrl[2];
} plcp_wla_Header_t;
typedef struct ctrl_Set_parm_s {
u8 Rate;
u8 Preamble;
u8 encryType;
u8 vapId;
//u8 bHwAppendMic;
u32 CurrFragLen;
u32 NextFragLen;
} ctrl_Set_parm_t;
typedef struct tuple_s
{
u8 ta[6]; //TA (Address 2)
u16 sn;
u8 fn;
u8 full;
} tuple_t;
typedef struct tuple_Cache_s
{
tuple_t cache[TUPLE_CACHE_SIZE];
u8 freeTpi;
} tuple_Cache_t;
typedef struct defrag_Mpdu_s
{
u8 ta[6];
u8 inUse;
u8 fn;
u32 eol;
u16 sn;
void *buf;
void *dataStart;
} defrag_Mpdu_t;
typedef struct defrag_Array_s
{
defrag_Mpdu_t mpdu[MAX_DEFRAG_NUM];
} defrag_Array_t;
/*Rx skb holding structure*/
struct rx_list_elem {
struct list_head list_elem;
dma_addr_t dma_addr;
struct sk_buff *skb;
#ifdef HOST_IF_USB
u32 UnFinishFrmLen;
#endif
}__attribute__ ((__packed__));
#define ZD1211_MAX_MTU 2400
#define MAX_EPINT_BUFFER 64
#define NUM_TCB 64//32
#define NUM_TBD_PER_TCB (2+MAX_SKB_FRAGS) //3
#define NUM_TBD (NUM_TCB * NUM_TBD_PER_TCB)
#define NUM_RFD 32
#ifdef HOST_IF_USB
// #define ZD1205_INT_MASK CFG_NEXT_BCN_EN | DTIM_NOTIFY_EN | WAKE_UP_EN
#define ZD1205_INT_MASK 0x4F0000
#else
#define ZD1205_INT_MASK TX_COMPLETE_EN | RX_COMPLETE_EN | RETRY_FAIL_EN | CFG_NEXT_BCN_EN | DTIM_NOTIFY_EN | WAKE_UP_EN | BUS_ABORT_EN
#endif
#define TX_RING_BYTES (NUM_TCB * (sizeof(zd1205_HwTCB_t) + sizeof(zd1205_Ctrl_Set_t) + sizeof(zd1205_Header_t)))+ (NUM_TBD * sizeof(zd1205_TBD_t))
#define ZD1205_REGS_SIZE 4096
#define ZD_RX_OFFSET 0x03
struct zdap_ioctl {
u16 cmd; /* Command to run */
u32 addr; /* Length of the data buffer */
u32 value; /* Pointer to the data buffer */
u8 data[0x100];
};
struct zd1205_private
{
//linux used
struct net_device *device;
#ifdef HOST_IF_USB
struct usb_device *usb;
int dev_index;
struct urb *ctrl_urb, *rx_urb, *tx_urb, *intr_urb, *reg_urb;
struct urb *read_urb, *write_urb; /* tmp urb pointer for rx_tasklet, tx_tasklet */
wait_queue_head_t regSet_wait;
wait_queue_head_t iorwRsp_wait;
wait_queue_head_t term_wait;
wait_queue_head_t msdelay;
struct semaphore ps_sem;
struct semaphore bcn_sem;
struct semaphore reg_sem;
struct semaphore config_sem;
struct semaphore ioctl_sem;
struct usb_interface *interface; /* the interface for this device */
spinlock_t intr_lock;
spinlock_t rx_pool_lock;
u8 tx_buff[MAX_WLAN_SIZE];
#if 1//(LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
u8 IntEPBuffer[MAX_EPINT_BUFFER];
#else
u8 *IntEPBuffer;
dma_addr_t IntBufferHandle;
#endif
u8 IntEPBuffer2[MAX_EPINT_BUFFER];
u8 IntEPBuffer3[MAX_EPINT_BUFFER];
u8 num_interrupt_in;
u8 num_interrupt_out;
u8 num_bulk_in;
u8 num_bulk_out;
u8 in_interval;
u8 out_interval;
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