AT91C_SPI1_TNCR.byteEndian=little
AT91C_SPI1_TNPR.name="AT91C_SPI1_TNPR"
AT91C_SPI1_TNPR.description="Transmit Next Pointer Register"
AT91C_SPI1_TNPR.helpkey="Transmit Next Pointer Register"
AT91C_SPI1_TNPR.access=memorymapped
AT91C_SPI1_TNPR.address=0xFFFE4118
AT91C_SPI1_TNPR.width=32
AT91C_SPI1_TNPR.byteEndian=little
AT91C_SPI1_PTCR.name="AT91C_SPI1_PTCR"
AT91C_SPI1_PTCR.description="PDC Transfer Control Register"
AT91C_SPI1_PTCR.helpkey="PDC Transfer Control Register"
AT91C_SPI1_PTCR.access=memorymapped
AT91C_SPI1_PTCR.address=0xFFFE4120
AT91C_SPI1_PTCR.width=32
AT91C_SPI1_PTCR.byteEndian=little
AT91C_SPI1_PTCR.type=enum
AT91C_SPI1_PTCR.enum.0.name=*** Write only ***
AT91C_SPI1_PTCR.enum.1.name=Error
# ========== Register definition for SPI1 peripheral ========== 
AT91C_SPI1_CSR.name="AT91C_SPI1_CSR"
AT91C_SPI1_CSR.description="Chip Select Register"
AT91C_SPI1_CSR.helpkey="Chip Select Register"
AT91C_SPI1_CSR.access=memorymapped
AT91C_SPI1_CSR.address=0xFFFE4030
AT91C_SPI1_CSR.width=32
AT91C_SPI1_CSR.byteEndian=little
AT91C_SPI1_IDR.name="AT91C_SPI1_IDR"
AT91C_SPI1_IDR.description="Interrupt Disable Register"
AT91C_SPI1_IDR.helpkey="Interrupt Disable Register"
AT91C_SPI1_IDR.access=memorymapped
AT91C_SPI1_IDR.address=0xFFFE4018
AT91C_SPI1_IDR.width=32
AT91C_SPI1_IDR.byteEndian=little
AT91C_SPI1_IDR.type=enum
AT91C_SPI1_IDR.enum.0.name=*** Write only ***
AT91C_SPI1_IDR.enum.1.name=Error
AT91C_SPI1_SR.name="AT91C_SPI1_SR"
AT91C_SPI1_SR.description="Status Register"
AT91C_SPI1_SR.helpkey="Status Register"
AT91C_SPI1_SR.access=memorymapped
AT91C_SPI1_SR.address=0xFFFE4010
AT91C_SPI1_SR.width=32
AT91C_SPI1_SR.byteEndian=little
AT91C_SPI1_SR.permission.write=none
AT91C_SPI1_RDR.name="AT91C_SPI1_RDR"
AT91C_SPI1_RDR.description="Receive Data Register"
AT91C_SPI1_RDR.helpkey="Receive Data Register"
AT91C_SPI1_RDR.access=memorymapped
AT91C_SPI1_RDR.address=0xFFFE4008
AT91C_SPI1_RDR.width=32
AT91C_SPI1_RDR.byteEndian=little
AT91C_SPI1_RDR.permission.write=none
AT91C_SPI1_CR.name="AT91C_SPI1_CR"
AT91C_SPI1_CR.description="Control Register"
AT91C_SPI1_CR.helpkey="Control Register"
AT91C_SPI1_CR.access=memorymapped
AT91C_SPI1_CR.address=0xFFFE4000
AT91C_SPI1_CR.width=32
AT91C_SPI1_CR.byteEndian=little
AT91C_SPI1_CR.permission.write=none
AT91C_SPI1_IMR.name="AT91C_SPI1_IMR"
AT91C_SPI1_IMR.description="Interrupt Mask Register"
AT91C_SPI1_IMR.helpkey="Interrupt Mask Register"
AT91C_SPI1_IMR.access=memorymapped
AT91C_SPI1_IMR.address=0xFFFE401C
AT91C_SPI1_IMR.width=32
AT91C_SPI1_IMR.byteEndian=little
AT91C_SPI1_IMR.permission.write=none
AT91C_SPI1_IER.name="AT91C_SPI1_IER"
AT91C_SPI1_IER.description="Interrupt Enable Register"
AT91C_SPI1_IER.helpkey="Interrupt Enable Register"
AT91C_SPI1_IER.access=memorymapped
AT91C_SPI1_IER.address=0xFFFE4014
AT91C_SPI1_IER.width=32
AT91C_SPI1_IER.byteEndian=little
AT91C_SPI1_IER.type=enum
AT91C_SPI1_IER.enum.0.name=*** Write only ***
AT91C_SPI1_IER.enum.1.name=Error
AT91C_SPI1_TDR.name="AT91C_SPI1_TDR"
AT91C_SPI1_TDR.description="Transmit Data Register"
AT91C_SPI1_TDR.helpkey="Transmit Data Register"
AT91C_SPI1_TDR.access=memorymapped
AT91C_SPI1_TDR.address=0xFFFE400C
AT91C_SPI1_TDR.width=32
AT91C_SPI1_TDR.byteEndian=little
AT91C_SPI1_TDR.type=enum
AT91C_SPI1_TDR.enum.0.name=*** Write only ***
AT91C_SPI1_TDR.enum.1.name=Error
AT91C_SPI1_MR.name="AT91C_SPI1_MR"
AT91C_SPI1_MR.description="Mode Register"
AT91C_SPI1_MR.helpkey="Mode Register"
AT91C_SPI1_MR.access=memorymapped
AT91C_SPI1_MR.address=0xFFFE4004
AT91C_SPI1_MR.width=32
AT91C_SPI1_MR.byteEndian=little
# ========== Register definition for PDC_SPI0 peripheral ========== 
AT91C_SPI0_PTCR.name="AT91C_SPI0_PTCR"
AT91C_SPI0_PTCR.description="PDC Transfer Control Register"
AT91C_SPI0_PTCR.helpkey="PDC Transfer Control Register"
AT91C_SPI0_PTCR.access=memorymapped
AT91C_SPI0_PTCR.address=0xFFFE0120
AT91C_SPI0_PTCR.width=32
AT91C_SPI0_PTCR.byteEndian=little
AT91C_SPI0_PTCR.type=enum
AT91C_SPI0_PTCR.enum.0.name=*** Write only ***
AT91C_SPI0_PTCR.enum.1.name=Error
AT91C_SPI0_TNPR.name="AT91C_SPI0_TNPR"
AT91C_SPI0_TNPR.description="Transmit Next Pointer Register"
AT91C_SPI0_TNPR.helpkey="Transmit Next Pointer Register"
AT91C_SPI0_TNPR.access=memorymapped
AT91C_SPI0_TNPR.address=0xFFFE0118
AT91C_SPI0_TNPR.width=32
AT91C_SPI0_TNPR.byteEndian=little
AT91C_SPI0_RNPR.name="AT91C_SPI0_RNPR"
AT91C_SPI0_RNPR.description="Receive Next Pointer Register"
AT91C_SPI0_RNPR.helpkey="Receive Next Pointer Register"
AT91C_SPI0_RNPR.access=memorymapped
AT91C_SPI0_RNPR.address=0xFFFE0110
AT91C_SPI0_RNPR.width=32
AT91C_SPI0_RNPR.byteEndian=little
AT91C_SPI0_TPR.name="AT91C_SPI0_TPR"
AT91C_SPI0_TPR.description="Transmit Pointer Register"
AT91C_SPI0_TPR.helpkey="Transmit Pointer Register"
AT91C_SPI0_TPR.access=memorymapped
AT91C_SPI0_TPR.address=0xFFFE0108
AT91C_SPI0_TPR.width=32
AT91C_SPI0_TPR.byteEndian=little
AT91C_SPI0_RPR.name="AT91C_SPI0_RPR"
AT91C_SPI0_RPR.description="Receive Pointer Register"
AT91C_SPI0_RPR.helpkey="Receive Pointer Register"
AT91C_SPI0_RPR.access=memorymapped
AT91C_SPI0_RPR.address=0xFFFE0100
AT91C_SPI0_RPR.width=32
AT91C_SPI0_RPR.byteEndian=little
AT91C_SPI0_PTSR.name="AT91C_SPI0_PTSR"
AT91C_SPI0_PTSR.description="PDC Transfer Status Register"
AT91C_SPI0_PTSR.helpkey="PDC Transfer Status Register"
AT91C_SPI0_PTSR.access=memorymapped
AT91C_SPI0_PTSR.address=0xFFFE0124
AT91C_SPI0_PTSR.width=32
AT91C_SPI0_PTSR.byteEndian=little
AT91C_SPI0_PTSR.permission.write=none
AT91C_SPI0_TNCR.name="AT91C_SPI0_TNCR"
AT91C_SPI0_TNCR.description="Transmit Next Counter Register"
AT91C_SPI0_TNCR.helpkey="Transmit Next Counter Register"
AT91C_SPI0_TNCR.access=memorymapped
AT91C_SPI0_TNCR.address=0xFFFE011C
AT91C_SPI0_TNCR.width=32
AT91C_SPI0_TNCR.byteEndian=little
AT91C_SPI0_RNCR.name="AT91C_SPI0_RNCR"
AT91C_SPI0_RNCR.description="Receive Next Counter Register"
AT91C_SPI0_RNCR.helpkey="Receive Next Counter Register"
AT91C_SPI0_RNCR.access=memorymapped
AT91C_SPI0_RNCR.address=0xFFFE0114
AT91C_SPI0_RNCR.width=32
AT91C_SPI0_RNCR.byteEndian=little
AT91C_SPI0_TCR.name="AT91C_SPI0_TCR"
AT91C_SPI0_TCR.description="Transmit Counter Register"
AT91C_SPI0_TCR.helpkey="Transmit Counter Register"
AT91C_SPI0_TCR.access=memorymapped
AT91C_SPI0_TCR.address=0xFFFE010C
AT91C_SPI0_TCR.width=32
AT91C_SPI0_TCR.byteEndian=little
AT91C_SPI0_RCR.name="AT91C_SPI0_RCR"
AT91C_SPI0_RCR.description="Receive Counter Register"
AT91C_SPI0_RCR.helpkey="Receive Counter Register"
AT91C_SPI0_RCR.access=memorymapped
AT91C_SPI0_RCR.address=0xFFFE0104
AT91C_SPI0_RCR.width=32
AT91C_SPI0_RCR.byteEndian=little
# ========== Register definition for SPI0 peripheral ========== 
AT91C_SPI0_CSR.name="AT91C_SPI0_CSR"
AT91C_SPI0_CSR.description="Chip Select Register"
AT91C_SPI0_CSR.helpkey="Chip Select Register"
AT91C_SPI0_CSR.access=memorymapped
AT91C_SPI0_CSR.address=0xFFFE0030
AT91C_SPI0_CSR.width=32
AT91C_SPI0_CSR.byteEndian=little
AT91C_SPI0_IDR.name="AT91C_SPI0_IDR"
AT91C_SPI0_IDR.description="Interrupt Disable Register"
AT91C_SPI0_IDR.helpkey="Interrupt Disable Register"
AT91C_SPI0_IDR.access=memorymapped
AT91C_SPI0_IDR.address=0xFFFE0018
AT91C_SPI0_IDR.width=32
AT91C_SPI0_IDR.byteEndian=little
AT91C_SPI0_IDR.type=enum
AT91C_SPI0_IDR.enum.0.name=*** Write only ***
AT91C_SPI0_IDR.enum.1.name=Error
AT91C_SPI0_SR.name="AT91C_SPI0_SR"
AT91C_SPI0_SR.description="Status Register"
AT91C_SPI0_SR.helpkey="Status Register"
AT91C_SPI0_SR.access=memorymapped
AT91C_SPI0_SR.address=0xFFFE0010
AT91C_SPI0_SR.width=32
AT91C_SPI0_SR.byteEndian=little
AT91C_SPI0_SR.permission.write=none
AT91C_SPI0_RDR.name="AT91C_SPI0_RDR"
AT91C_SPI0_RDR.description="Receive Data Register"
AT91C_SPI0_RDR.helpkey="Receive Data Register"
AT91C_SPI0_RDR.access=memorymapped
AT91C_SPI0_RDR.address=0xFFFE0008
AT91C_SPI0_RDR.width=32
AT91C_SPI0_RDR.byteEndian=little
AT91C_SPI0_RDR.permission.write=none
AT91C_SPI0_CR.name="AT91C_SPI0_CR"
AT91C_SPI0_CR.description="Control Register"
AT91C_SPI0_CR.helpkey="Control Register"
AT91C_SPI0_CR.access=memorymapped
AT91C_SPI0_CR.address=0xFFFE0000
AT91C_SPI0_CR.width=32
AT91C_SPI0_CR.byteEndian=little
AT91C_SPI0_CR.permission.write=none
AT91C_SPI0_IMR.name="AT91C_SPI0_IMR"
AT91C_SPI0_IMR.description="Interrupt Mask Register"
AT91C_SPI0_IMR.helpkey="Interrupt Mask Register"
AT91C_SPI0_IMR.access=memorymapped
AT91C_SPI0_IMR.address=0xFFFE001C
AT91C_SPI0_IMR.width=32
AT91C_SPI0_IMR.byteEndian=little
AT91C_SPI0_IMR.permission.write=none
AT91C_SPI0_IER.name="AT91C_SPI0_IER"
AT91C_SPI0_IER.description="Interrupt Enable Register"
AT91C_SPI0_IER.helpkey="Interrupt Enable Register"
AT91C_SPI0_IER.access=memorymapped
AT91C_SPI0_IER.address=0xFFFE0014
AT91C_SPI0_IER.width=32
AT91C_SPI0_IER.byteEndian=little
AT91C_SPI0_IER.type=enum
AT91C_SPI0_IER.enum.0.name=*** Write only ***
AT91C_SPI0_IER.enum.1.name=Error
AT91C_SPI0_TDR.name="AT91C_SPI0_TDR"
AT91C_SPI0_TDR.description="Transmit Data Register"
AT91C_SPI0_TDR.helpkey="Transmit Data Register"
AT91C_SPI0_TDR.access=memorymapped
AT91C_SPI0_TDR.address=0xFFFE000C
AT91C_SPI0_TDR.width=32
AT91C_SPI0_TDR.byteEndian=little
AT91C_SPI0_TDR.type=enum
AT91C_SPI0_TDR.enum.0.name=*** Write only ***
AT91C_SPI0_TDR.enum.1.name=Error
AT91C_SPI0_MR.name="AT91C_SPI0_MR"
AT91C_SPI0_MR.description="Mode Register"
AT91C_SPI0_MR.helpkey="Mode Register"
AT91C_SPI0_MR.access=memorymapped
AT91C_SPI0_MR.address=0xFFFE0004
AT91C_SPI0_MR.width=32
AT91C_SPI0_MR.byteEndian=little
# ========== Register definition for PDC_US1 peripheral ========== 
AT91C_US1_PTSR.name="AT91C_US1_PTSR"
AT91C_US1_PTSR.description="PDC Transfer Status Register"
AT91C_US1_PTSR.helpkey="PDC Transfer Status Register"
AT91C_US1_PTSR.access=memorymapped
AT91C_US1_PTSR.address=0xFFFC4124
AT91C_US1_PTSR.width=32
AT91C_US1_PTSR.byteEndian=little
AT91C_US1_PTSR.permission.write=none
AT91C_US1_TNCR.name="AT91C_US1_TNCR"
AT91C_US1_TNCR.description="Transmit Next Counter Register"
AT91C_US1_TNCR.helpkey="Transmit Next Counter Register"
AT91C_US1_TNCR.access=memorymapped
AT91C_US1_TNCR.address=0xFFFC411C
AT91C_US1_TNCR.width=32
AT91C_US1_TNCR.byteEndian=little
AT91C_US1_RNCR.name="AT91C_US1_RNCR"
AT91C_US1_RNCR.description="Receive Next Counter Register"
AT91C_US1_RNCR.helpkey="Receive Next Counter Register"
AT91C_US1_RNCR.access=memorymapped
AT91C_US1_RNCR.address=0xFFFC4114
AT91C_US1_RNCR.width=32
AT91C_US1_RNCR.byteEndian=little
AT91C_US1_TCR.name="AT91C_US1_TCR"
AT91C_US1_TCR.description="Transmit Counter Register"
AT91C_US1_TCR.helpkey="Transmit Counter Register"
AT91C_US1_TCR.access=memorymapped
AT91C_US1_TCR.address=0xFFFC410C
AT91C_US1_TCR.width=32
AT91C_US1_TCR.byteEndian=little
AT91C_US1_RCR.name="AT91C_US1_RCR"
AT91C_US1_RCR.description="Receive Counter Register"
AT91C_US1_RCR.helpkey="Receive Counter Register"
AT91C_US1_RCR.access=memorymapped
AT91C_US1_RCR.address=0xFFFC4104
AT91C_US1_RCR.width=32
AT91C_US1_RCR.byteEndian=little
AT91C_US1_PTCR.name="AT91C_US1_PTCR"
AT91C_US1_PTCR.description="PDC Transfer Control Register"
AT91C_US1_PTCR.helpkey="PDC Transfer Control Register"
AT91C_US1_PTCR.access=memorymapped
AT91C_US1_PTCR.address=0xFFFC4120
AT91C_US1_PTCR.width=32
AT91C_US1_PTCR.byteEndian=little
AT91C_US1_PTCR.type=enum
AT91C_US1_PTCR.enum.0.name=*** Write only ***
AT91C_US1_PTCR.enum.1.name=Error
AT91C_US1_TNPR.name="AT91C_US1_TNPR"
AT91C_US1_TNPR.description="Transmit Next Pointer Register"
AT91C_US1_TNPR.helpkey="Transmit Next Pointer Register"
AT91C_US1_TNPR.access=memorymapped
AT91C_US1_TNPR.address=0xFFFC4118
AT91C_US1_TNPR.width=32
AT91C_US1_TNPR.byteEndian=little
AT91C_US1_RNPR.name="AT91C_US1_RNPR"
AT91C_US1_RNPR.description="Receive Next Pointer Register"
AT91C_US1_RNPR.helpkey="Receive Next Pointer Register"
AT91C_US1_RNPR.access=memorymapped
AT91C_US1_RNPR.address=0xFFFC4110
AT91C_US1_RNPR.width=32
AT91C_US1_RNPR.byteEndian=little
AT91C_US1_TPR.name="AT91C_US1_TPR"
AT91C_US1_TPR.description="Transmit Pointer Register"
AT91C_US1_TPR.helpkey="Transmit Pointer Register"
AT91C_US1_TPR.access=memorymapped
AT91C_US1_TPR.address=0xFFFC4108
AT91C_US1_TPR.width=32
AT91C_US1_TPR.byteEndian=little
AT91C_US1_RPR.name="AT91C_US1_RPR"
AT91C_US1_RPR.description="Receive Pointer Register"
AT91C_US1_RPR.helpkey="Receive Pointer Register"
AT91C_US1_RPR.access=memorymapped
AT91C_US1_RPR.address=0xFFFC4100
AT91C_US1_RPR.width=32
AT91C_US1_RPR.byteEndian=little
# ========== Register definition for US1 peripheral ========== 
AT91C_US1_RHR.name="AT91C_US1_RHR"
AT91C_US1_RHR.description="Receiver Holding Register"
AT91C_US1_RHR.helpkey="Rece