?? at91sam7x256.tcl
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# ----------------------------------------------------------------------------
# ATMEL Microcontroller Software Support - ROUSSET -
# ----------------------------------------------------------------------------
# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# ----------------------------------------------------------------------------
# File Name : AT91SAM7X256.tcl
# Object : AT91SAM7X256 definitions
# Generated : AT91 SW Application Group 09/12/2005 (15:39:19)
#
# CVS Reference : /AT91SAM7X256.pl/1.14/Mon Sep 12 12:28:34 2005//
# CVS Reference : /SYS_SAM7X.pl/1.3/Wed Feb 2 15:48:15 2005//
# CVS Reference : /MC_SAM7X.pl/1.2/Fri May 20 14:22:29 2005//
# CVS Reference : /PMC_SAM7X.pl/1.4/Tue Feb 8 14:00:19 2005//
# CVS Reference : /RSTC_SAM7X.pl/1.2/Wed Jul 13 15:25:17 2005//
# CVS Reference : /UDP_SAM7X.pl/1.1/Tue May 10 12:39:23 2005//
# CVS Reference : /PWM_SAM7X.pl/1.1/Tue May 10 12:38:54 2005//
# CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
# CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
# CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
# CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
# CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
# CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:40:38 2005//
# CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
# CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
# CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
# CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
# CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
# CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
# CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
# CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005//
# CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
# CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
# CVS Reference : /AES_6149A.pl/1.10/Mon Feb 7 09:46:08 2005//
# CVS Reference : /DES3_6150A.pl/1.1/Mon Jan 17 13:30:33 2005//
# ----------------------------------------------------------------------------
# *****************************************************************************
# SOFTWARE API DEFINITION FOR System Peripherals
# *****************************************************************************
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
# *****************************************************************************
# -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
set AT91C_AIC_PRIOR [expr 0x7 << 0 ]
set AT91C_AIC_PRIOR_LOWEST 0x0
set AT91C_AIC_PRIOR_HIGHEST 0x7
set AT91C_AIC_SRCTYPE [expr 0x3 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL [expr 0x0 << 5 ]
set AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL [expr 0x0 << 5 ]
set AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE [expr 0x1 << 5 ]
set AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE [expr 0x1 << 5 ]
set AT91C_AIC_SRCTYPE_HIGH_LEVEL [expr 0x2 << 5 ]
set AT91C_AIC_SRCTYPE_POSITIVE_EDGE [expr 0x3 << 5 ]
# -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
set AT91C_AIC_NFIQ [expr 0x1 << 0 ]
set AT91C_AIC_NIRQ [expr 0x1 << 1 ]
# -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
set AT91C_AIC_DCR_PROT [expr 0x1 << 0 ]
set AT91C_AIC_DCR_GMSK [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Peripheral DMA Controller
# *****************************************************************************
# -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_RXTDIS [expr 0x1 << 1 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
set AT91C_PDC_TXTDIS [expr 0x1 << 9 ]
# -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
set AT91C_PDC_RXTEN [expr 0x1 << 0 ]
set AT91C_PDC_TXTEN [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Debug Unit
# *****************************************************************************
# -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
set AT91C_US_RSTRX [expr 0x1 << 2 ]
set AT91C_US_RSTTX [expr 0x1 << 3 ]
set AT91C_US_RXEN [expr 0x1 << 4 ]
set AT91C_US_RXDIS [expr 0x1 << 5 ]
set AT91C_US_TXEN [expr 0x1 << 6 ]
set AT91C_US_TXDIS [expr 0x1 << 7 ]
set AT91C_US_RSTSTA [expr 0x1 << 8 ]
# -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
set AT91C_US_PAR [expr 0x7 << 9 ]
set AT91C_US_PAR_EVEN [expr 0x0 << 9 ]
set AT91C_US_PAR_ODD [expr 0x1 << 9 ]
set AT91C_US_PAR_SPACE [expr 0x2 << 9 ]
set AT91C_US_PAR_MARK [expr 0x3 << 9 ]
set AT91C_US_PAR_NONE [expr 0x4 << 9 ]
set AT91C_US_PAR_MULTI_DROP [expr 0x6 << 9 ]
set AT91C_US_CHMODE [expr 0x3 << 14 ]
set AT91C_US_CHMODE_NORMAL [expr 0x0 << 14 ]
set AT91C_US_CHMODE_AUTO [expr 0x1 << 14 ]
set AT91C_US_CHMODE_LOCAL [expr 0x2 << 14 ]
set AT91C_US_CHMODE_REMOTE [expr 0x3 << 14 ]
# -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_COMM_TX [expr 0x1 << 30 ]
set AT91C_US_COMM_RX [expr 0x1 << 31 ]
# -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
set AT91C_US_FORCE_NTRST [expr 0x1 << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Parallel Input Output Controler
# *****************************************************************************
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Clock Generator Controler
# *****************************************************************************
# -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
set AT91C_CKGR_MOSCEN [expr 0x1 << 0 ]
set AT91C_CKGR_OSCBYPASS [expr 0x1 << 1 ]
set AT91C_CKGR_OSCOUNT [expr 0xFF << 8 ]
# -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
set AT91C_CKGR_MAINF [expr 0xFFFF << 0 ]
set AT91C_CKGR_MAINRDY [expr 0x1 << 16 ]
# -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
set AT91C_CKGR_DIV [expr 0xFF << 0 ]
set AT91C_CKGR_DIV_0 0x0
set AT91C_CKGR_DIV_BYPASS 0x1
set AT91C_CKGR_PLLCOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUT [expr 0x3 << 14 ]
set AT91C_CKGR_OUT_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUT_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUT_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUT_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MUL [expr 0x7FF << 16 ]
set AT91C_CKGR_USBDIV [expr 0x3 << 28 ]
set AT91C_CKGR_USBDIV_0 [expr 0x0 << 28 ]
set AT91C_CKGR_USBDIV_1 [expr 0x1 << 28 ]
set AT91C_CKGR_USBDIV_2 [expr 0x2 << 28 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Power Management Controler
# *****************************************************************************
# -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_PCK2 [expr 0x1 << 10 ]
set AT91C_PMC_PCK3 [expr 0x1 << 11 ]
# -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_PCK2 [expr 0x1 << 10 ]
set AT91C_PMC_PCK3 [expr 0x1 << 11 ]
# -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
set AT91C_PMC_PCK [expr 0x1 << 0 ]
set AT91C_PMC_UDP [expr 0x1 << 7 ]
set AT91C_PMC_PCK0 [expr 0x1 << 8 ]
set AT91C_PMC_PCK1 [expr 0x1 << 9 ]
set AT91C_PMC_PCK2 [expr 0x1 << 10 ]
set AT91C_PMC_PCK3 [expr 0x1 << 11 ]
# -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
set AT91C_CKGR_MOSCEN [expr 0x1 << 0 ]
set AT91C_CKGR_OSCBYPASS [expr 0x1 << 1 ]
set AT91C_CKGR_OSCOUNT [expr 0xFF << 8 ]
# -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
set AT91C_CKGR_MAINF [expr 0xFFFF << 0 ]
set AT91C_CKGR_MAINRDY [expr 0x1 << 16 ]
# -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
set AT91C_CKGR_DIV [expr 0xFF << 0 ]
set AT91C_CKGR_DIV_0 0x0
set AT91C_CKGR_DIV_BYPASS 0x1
set AT91C_CKGR_PLLCOUNT [expr 0x3F << 8 ]
set AT91C_CKGR_OUT [expr 0x3 << 14 ]
set AT91C_CKGR_OUT_0 [expr 0x0 << 14 ]
set AT91C_CKGR_OUT_1 [expr 0x1 << 14 ]
set AT91C_CKGR_OUT_2 [expr 0x2 << 14 ]
set AT91C_CKGR_OUT_3 [expr 0x3 << 14 ]
set AT91C_CKGR_MUL [expr 0x7FF << 16 ]
set AT91C_CKGR_USBDIV [expr 0x3 << 28 ]
set AT91C_CKGR_USBDIV_0 [expr 0x0 << 28 ]
set AT91C_CKGR_USBDIV_1 [expr 0x1 << 28 ]
set AT91C_CKGR_USBDIV_2 [expr 0x2 << 28 ]
# -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
set AT91C_PMC_CSS [expr 0x3 << 0 ]
set AT91C_PMC_CSS_SLOW_CLK 0x0
set AT91C_PMC_CSS_MAIN_CLK 0x1
set AT91C_PMC_CSS_PLL_CLK 0x3
set AT91C_PMC_PRES [expr 0x7 << 2 ]
set AT91C_PMC_PRES_CLK [expr 0x0 << 2 ]
set AT91C_PMC_PRES_CLK_2 [expr 0x1 << 2 ]
set AT91C_PMC_PRES_CLK_4 [expr 0x2 << 2 ]
set AT91C_PMC_PRES_CLK_8 [expr 0x3 << 2 ]
set AT91C_PMC_PRES_CLK_16 [expr 0x4 << 2 ]
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