?? at91sam7x256.tcl
字號:
set AT91C_PMC_PRES_CLK_32 [expr 0x5 << 2 ]
set AT91C_PMC_PRES_CLK_64 [expr 0x6 << 2 ]
# -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
set AT91C_PMC_CSS [expr 0x3 << 0 ]
set AT91C_PMC_CSS_SLOW_CLK 0x0
set AT91C_PMC_CSS_MAIN_CLK 0x1
set AT91C_PMC_CSS_PLL_CLK 0x3
set AT91C_PMC_PRES [expr 0x7 << 2 ]
set AT91C_PMC_PRES_CLK [expr 0x0 << 2 ]
set AT91C_PMC_PRES_CLK_2 [expr 0x1 << 2 ]
set AT91C_PMC_PRES_CLK_4 [expr 0x2 << 2 ]
set AT91C_PMC_PRES_CLK_8 [expr 0x3 << 2 ]
set AT91C_PMC_PRES_CLK_16 [expr 0x4 << 2 ]
set AT91C_PMC_PRES_CLK_32 [expr 0x5 << 2 ]
set AT91C_PMC_PRES_CLK_64 [expr 0x6 << 2 ]
# -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCK [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
set AT91C_PMC_PCK2RDY [expr 0x1 << 10 ]
set AT91C_PMC_PCK3RDY [expr 0x1 << 11 ]
# -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCK [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
set AT91C_PMC_PCK2RDY [expr 0x1 << 10 ]
set AT91C_PMC_PCK3RDY [expr 0x1 << 11 ]
# -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCK [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
set AT91C_PMC_PCK2RDY [expr 0x1 << 10 ]
set AT91C_PMC_PCK3RDY [expr 0x1 << 11 ]
# -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
set AT91C_PMC_MOSCS [expr 0x1 << 0 ]
set AT91C_PMC_LOCK [expr 0x1 << 2 ]
set AT91C_PMC_MCKRDY [expr 0x1 << 3 ]
set AT91C_PMC_PCK0RDY [expr 0x1 << 8 ]
set AT91C_PMC_PCK1RDY [expr 0x1 << 9 ]
set AT91C_PMC_PCK2RDY [expr 0x1 << 10 ]
set AT91C_PMC_PCK3RDY [expr 0x1 << 11 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Reset Controller Interface
# *****************************************************************************
# -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
set AT91C_RSTC_PROCRST [expr 0x1 << 0 ]
set AT91C_RSTC_PERRST [expr 0x1 << 2 ]
set AT91C_RSTC_EXTRST [expr 0x1 << 3 ]
set AT91C_RSTC_KEY [expr 0xFF << 24 ]
# -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
set AT91C_RSTC_URSTS [expr 0x1 << 0 ]
set AT91C_RSTC_BODSTS [expr 0x1 << 1 ]
set AT91C_RSTC_RSTTYP [expr 0x7 << 8 ]
set AT91C_RSTC_RSTTYP_POWERUP [expr 0x0 << 8 ]
set AT91C_RSTC_RSTTYP_WAKEUP [expr 0x1 << 8 ]
set AT91C_RSTC_RSTTYP_WATCHDOG [expr 0x2 << 8 ]
set AT91C_RSTC_RSTTYP_SOFTWARE [expr 0x3 << 8 ]
set AT91C_RSTC_RSTTYP_USER [expr 0x4 << 8 ]
set AT91C_RSTC_RSTTYP_BROWNOUT [expr 0x5 << 8 ]
set AT91C_RSTC_NRSTL [expr 0x1 << 16 ]
set AT91C_RSTC_SRCMP [expr 0x1 << 17 ]
# -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
set AT91C_RSTC_URSTEN [expr 0x1 << 0 ]
set AT91C_RSTC_URSTIEN [expr 0x1 << 4 ]
set AT91C_RSTC_ERSTL [expr 0xF << 8 ]
set AT91C_RSTC_BODIEN [expr 0x1 << 16 ]
set AT91C_RSTC_KEY [expr 0xFF << 24 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
# *****************************************************************************
# -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
set AT91C_RTTC_RTPRES [expr 0xFFFF << 0 ]
set AT91C_RTTC_ALMIEN [expr 0x1 << 16 ]
set AT91C_RTTC_RTTINCIEN [expr 0x1 << 17 ]
set AT91C_RTTC_RTTRST [expr 0x1 << 18 ]
# -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
set AT91C_RTTC_ALMV [expr 0x0 << 0 ]
# -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
set AT91C_RTTC_CRTV [expr 0x0 << 0 ]
# -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
set AT91C_RTTC_ALMS [expr 0x1 << 0 ]
set AT91C_RTTC_RTTINC [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
# *****************************************************************************
# -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
set AT91C_PITC_PIV [expr 0xFFFFF << 0 ]
set AT91C_PITC_PITEN [expr 0x1 << 24 ]
set AT91C_PITC_PITIEN [expr 0x1 << 25 ]
# -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
set AT91C_PITC_PITS [expr 0x1 << 0 ]
# -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
set AT91C_PITC_CPIV [expr 0xFFFFF << 0 ]
set AT91C_PITC_PICNT [expr 0xFFF << 20 ]
# -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
set AT91C_PITC_CPIV [expr 0xFFFFF << 0 ]
set AT91C_PITC_PICNT [expr 0xFFF << 20 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
# *****************************************************************************
# -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
set AT91C_WDTC_WDRSTT [expr 0x1 << 0 ]
set AT91C_WDTC_KEY [expr 0xFF << 24 ]
# -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
set AT91C_WDTC_WDV [expr 0xFFF << 0 ]
set AT91C_WDTC_WDFIEN [expr 0x1 << 12 ]
set AT91C_WDTC_WDRSTEN [expr 0x1 << 13 ]
set AT91C_WDTC_WDRPROC [expr 0x1 << 14 ]
set AT91C_WDTC_WDDIS [expr 0x1 << 15 ]
set AT91C_WDTC_WDD [expr 0xFFF << 16 ]
set AT91C_WDTC_WDDBGHLT [expr 0x1 << 28 ]
set AT91C_WDTC_WDIDLEHLT [expr 0x1 << 29 ]
# -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
set AT91C_WDTC_WDUNF [expr 0x1 << 0 ]
set AT91C_WDTC_WDERR [expr 0x1 << 1 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
# *****************************************************************************
# -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
set AT91C_VREG_PSTDBY [expr 0x1 << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Memory Controller Interface
# *****************************************************************************
# -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
set AT91C_MC_RCB [expr 0x1 << 0 ]
# -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
set AT91C_MC_UNDADD [expr 0x1 << 0 ]
set AT91C_MC_MISADD [expr 0x1 << 1 ]
set AT91C_MC_ABTSZ [expr 0x3 << 8 ]
set AT91C_MC_ABTSZ_BYTE [expr 0x0 << 8 ]
set AT91C_MC_ABTSZ_HWORD [expr 0x1 << 8 ]
set AT91C_MC_ABTSZ_WORD [expr 0x2 << 8 ]
set AT91C_MC_ABTTYP [expr 0x3 << 10 ]
set AT91C_MC_ABTTYP_DATAR [expr 0x0 << 10 ]
set AT91C_MC_ABTTYP_DATAW [expr 0x1 << 10 ]
set AT91C_MC_ABTTYP_FETCH [expr 0x2 << 10 ]
set AT91C_MC_MST0 [expr 0x1 << 16 ]
set AT91C_MC_MST1 [expr 0x1 << 17 ]
set AT91C_MC_SVMST0 [expr 0x1 << 24 ]
set AT91C_MC_SVMST1 [expr 0x1 << 25 ]
# -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
set AT91C_MC_FRDY [expr 0x1 << 0 ]
set AT91C_MC_LOCKE [expr 0x1 << 2 ]
set AT91C_MC_PROGE [expr 0x1 << 3 ]
set AT91C_MC_NEBP [expr 0x1 << 7 ]
set AT91C_MC_FWS [expr 0x3 << 8 ]
set AT91C_MC_FWS_0FWS [expr 0x0 << 8 ]
set AT91C_MC_FWS_1FWS [expr 0x1 << 8 ]
set AT91C_MC_FWS_2FWS [expr 0x2 << 8 ]
set AT91C_MC_FWS_3FWS [expr 0x3 << 8 ]
set AT91C_MC_FMCN [expr 0xFF << 16 ]
# -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
set AT91C_MC_FCMD [expr 0xF << 0 ]
set AT91C_MC_FCMD_START_PROG 0x1
set AT91C_MC_FCMD_LOCK 0x2
set AT91C_MC_FCMD_PROG_AND_LOCK 0x3
set AT91C_MC_FCMD_UNLOCK 0x4
set AT91C_MC_FCMD_ERASE_ALL 0x8
set AT91C_MC_FCMD_SET_GP_NVM 0xB
set AT91C_MC_FCMD_CLR_GP_NVM 0xD
set AT91C_MC_FCMD_SET_SECURITY 0xF
set AT91C_MC_PAGEN [expr 0x3FF << 8 ]
set AT91C_MC_KEY [expr 0xFF << 24 ]
# -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
set AT91C_MC_FRDY [expr 0x1 << 0 ]
set AT91C_MC_LOCKE [expr 0x1 << 2 ]
set AT91C_MC_PROGE [expr 0x1 << 3 ]
set AT91C_MC_SECURITY [expr 0x1 << 4 ]
set AT91C_MC_GPNVM0 [expr 0x1 << 8 ]
set AT91C_MC_GPNVM1 [expr 0x1 << 9 ]
set AT91C_MC_GPNVM2 [expr 0x1 << 10 ]
set AT91C_MC_GPNVM3 [expr 0x1 << 11 ]
set AT91C_MC_GPNVM4 [expr 0x1 << 12 ]
set AT91C_MC_GPNVM5 [expr 0x1 << 13 ]
set AT91C_MC_GPNVM6 [expr 0x1 << 14 ]
set AT91C_MC_GPNVM7 [expr 0x1 << 15 ]
set AT91C_MC_LOCKS0 [expr 0x1 << 16 ]
set AT91C_MC_LOCKS1 [expr 0x1 << 17 ]
set AT91C_MC_LOCKS2 [expr 0x1 << 18 ]
set AT91C_MC_LOCKS3 [expr 0x1 << 19 ]
set AT91C_MC_LOCKS4 [expr 0x1 << 20 ]
set AT91C_MC_LOCKS5 [expr 0x1 << 21 ]
set AT91C_MC_LOCKS6 [expr 0x1 << 22 ]
set AT91C_MC_LOCKS7 [expr 0x1 << 23 ]
set AT91C_MC_LOCKS8 [expr 0x1 << 24 ]
set AT91C_MC_LOCKS9 [expr 0x1 << 25 ]
set AT91C_MC_LOCKS10 [expr 0x1 << 26 ]
set AT91C_MC_LOCKS11 [expr 0x1 << 27 ]
set AT91C_MC_LOCKS12 [expr 0x1 << 28 ]
set AT91C_MC_LOCKS13 [expr 0x1 << 29 ]
set AT91C_MC_LOCKS14 [expr 0x1 << 30 ]
set AT91C_MC_LOCKS15 [expr 0x1 << 31 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Serial Parallel Interface
# *****************************************************************************
# -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
set AT91C_SPI_SPIEN [expr 0x1 << 0 ]
set AT91C_SPI_SPIDIS [expr 0x1 << 1 ]
set AT91C_SPI_SWRST [expr 0x1 << 7 ]
set AT91C_SPI_LASTXFER [expr 0x1 << 24 ]
# -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
set AT91C_SPI_MSTR [expr 0x1 << 0 ]
set AT91C_SPI_PS [expr 0x1 << 1 ]
set AT91C_SPI_PS_FIXED [expr 0x0 << 1 ]
set AT91C_SPI_PS_VARIABLE [expr 0x1 << 1 ]
set AT91C_SPI_PCSDEC [expr 0x1 << 2 ]
set AT91C_SPI_FDIV [expr 0x1 << 3 ]
set AT91C_SPI_MODFDIS [expr 0x1 << 4 ]
set AT91C_SPI_LLB [expr 0x1 << 7 ]
set AT91C_SPI_PCS [expr 0xF << 16 ]
set AT91C_SPI_DLYBCS [expr 0xFF << 24 ]
# -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
set AT91C_SPI_RD [expr 0xFFFF << 0 ]
set AT91C_SPI_RPCS [expr 0xF << 16 ]
# -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
set AT91C_SPI_TD [expr 0xFFFF << 0 ]
set AT91C_SPI_TPCS [expr 0xF << 16 ]
set AT91C_SPI_LASTXFER [expr 0x1 << 24 ]
# -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
set AT91C_SPI_RDRF [expr 0x1 << 0 ]
set AT91C_SPI_TDRE [expr 0x1 << 1 ]
set AT91C_SPI_MODF [expr 0x1 << 2 ]
set AT91C_SPI_OVRES [expr 0x1 << 3 ]
set AT91C_SPI_ENDRX [expr 0x1 << 4 ]
set AT91C_SPI_ENDTX [expr 0x1 << 5 ]
set AT91C_SPI_RXBUFF [expr 0x1 << 6 ]
set AT91C_SPI_TXBUFE [expr 0x1 << 7 ]
set AT91C_SPI_NSSR [expr 0x1 << 8 ]
set AT91C_SPI_TXEMPTY [expr 0x1 << 9 ]
set AT91C_SPI_SPIENS [expr 0x1 << 16 ]
# -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
set AT91C_SPI_RDRF [expr 0x1 << 0 ]
set AT91C_SPI_TDRE [expr 0x1 << 1 ]
set AT91C_SPI_MODF [expr 0x1 << 2 ]
set AT91C_SPI_OVRES [expr 0x1 << 3 ]
set AT91C_SPI_ENDRX [expr 0x1 << 4 ]
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