?? at91sam7x256.tcl
字號(hào):
set AT91C_SPI_ENDTX [expr 0x1 << 5 ]
set AT91C_SPI_RXBUFF [expr 0x1 << 6 ]
set AT91C_SPI_TXBUFE [expr 0x1 << 7 ]
set AT91C_SPI_NSSR [expr 0x1 << 8 ]
set AT91C_SPI_TXEMPTY [expr 0x1 << 9 ]
# -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
set AT91C_SPI_RDRF [expr 0x1 << 0 ]
set AT91C_SPI_TDRE [expr 0x1 << 1 ]
set AT91C_SPI_MODF [expr 0x1 << 2 ]
set AT91C_SPI_OVRES [expr 0x1 << 3 ]
set AT91C_SPI_ENDRX [expr 0x1 << 4 ]
set AT91C_SPI_ENDTX [expr 0x1 << 5 ]
set AT91C_SPI_RXBUFF [expr 0x1 << 6 ]
set AT91C_SPI_TXBUFE [expr 0x1 << 7 ]
set AT91C_SPI_NSSR [expr 0x1 << 8 ]
set AT91C_SPI_TXEMPTY [expr 0x1 << 9 ]
# -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
set AT91C_SPI_RDRF [expr 0x1 << 0 ]
set AT91C_SPI_TDRE [expr 0x1 << 1 ]
set AT91C_SPI_MODF [expr 0x1 << 2 ]
set AT91C_SPI_OVRES [expr 0x1 << 3 ]
set AT91C_SPI_ENDRX [expr 0x1 << 4 ]
set AT91C_SPI_ENDTX [expr 0x1 << 5 ]
set AT91C_SPI_RXBUFF [expr 0x1 << 6 ]
set AT91C_SPI_TXBUFE [expr 0x1 << 7 ]
set AT91C_SPI_NSSR [expr 0x1 << 8 ]
set AT91C_SPI_TXEMPTY [expr 0x1 << 9 ]
# -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
set AT91C_SPI_CPOL [expr 0x1 << 0 ]
set AT91C_SPI_NCPHA [expr 0x1 << 1 ]
set AT91C_SPI_CSAAT [expr 0x1 << 3 ]
set AT91C_SPI_BITS [expr 0xF << 4 ]
set AT91C_SPI_BITS_8 [expr 0x0 << 4 ]
set AT91C_SPI_BITS_9 [expr 0x1 << 4 ]
set AT91C_SPI_BITS_10 [expr 0x2 << 4 ]
set AT91C_SPI_BITS_11 [expr 0x3 << 4 ]
set AT91C_SPI_BITS_12 [expr 0x4 << 4 ]
set AT91C_SPI_BITS_13 [expr 0x5 << 4 ]
set AT91C_SPI_BITS_14 [expr 0x6 << 4 ]
set AT91C_SPI_BITS_15 [expr 0x7 << 4 ]
set AT91C_SPI_BITS_16 [expr 0x8 << 4 ]
set AT91C_SPI_SCBR [expr 0xFF << 8 ]
set AT91C_SPI_DLYBS [expr 0xFF << 16 ]
set AT91C_SPI_DLYBCT [expr 0xFF << 24 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Usart
# *****************************************************************************
# -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
set AT91C_US_RSTRX [expr 0x1 << 2 ]
set AT91C_US_RSTTX [expr 0x1 << 3 ]
set AT91C_US_RXEN [expr 0x1 << 4 ]
set AT91C_US_RXDIS [expr 0x1 << 5 ]
set AT91C_US_TXEN [expr 0x1 << 6 ]
set AT91C_US_TXDIS [expr 0x1 << 7 ]
set AT91C_US_RSTSTA [expr 0x1 << 8 ]
set AT91C_US_STTBRK [expr 0x1 << 9 ]
set AT91C_US_STPBRK [expr 0x1 << 10 ]
set AT91C_US_STTTO [expr 0x1 << 11 ]
set AT91C_US_SENDA [expr 0x1 << 12 ]
set AT91C_US_RSTIT [expr 0x1 << 13 ]
set AT91C_US_RSTNACK [expr 0x1 << 14 ]
set AT91C_US_RETTO [expr 0x1 << 15 ]
set AT91C_US_DTREN [expr 0x1 << 16 ]
set AT91C_US_DTRDIS [expr 0x1 << 17 ]
set AT91C_US_RTSEN [expr 0x1 << 18 ]
set AT91C_US_RTSDIS [expr 0x1 << 19 ]
# -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
set AT91C_US_USMODE [expr 0xF << 0 ]
set AT91C_US_USMODE_NORMAL 0x0
set AT91C_US_USMODE_RS485 0x1
set AT91C_US_USMODE_HWHSH 0x2
set AT91C_US_USMODE_MODEM 0x3
set AT91C_US_USMODE_ISO7816_0 0x4
set AT91C_US_USMODE_ISO7816_1 0x6
set AT91C_US_USMODE_IRDA 0x8
set AT91C_US_USMODE_SWHSH 0xC
set AT91C_US_CLKS [expr 0x3 << 4 ]
set AT91C_US_CLKS_CLOCK [expr 0x0 << 4 ]
set AT91C_US_CLKS_FDIV1 [expr 0x1 << 4 ]
set AT91C_US_CLKS_SLOW [expr 0x2 << 4 ]
set AT91C_US_CLKS_EXT [expr 0x3 << 4 ]
set AT91C_US_CHRL [expr 0x3 << 6 ]
set AT91C_US_CHRL_5_BITS [expr 0x0 << 6 ]
set AT91C_US_CHRL_6_BITS [expr 0x1 << 6 ]
set AT91C_US_CHRL_7_BITS [expr 0x2 << 6 ]
set AT91C_US_CHRL_8_BITS [expr 0x3 << 6 ]
set AT91C_US_SYNC [expr 0x1 << 8 ]
set AT91C_US_PAR [expr 0x7 << 9 ]
set AT91C_US_PAR_EVEN [expr 0x0 << 9 ]
set AT91C_US_PAR_ODD [expr 0x1 << 9 ]
set AT91C_US_PAR_SPACE [expr 0x2 << 9 ]
set AT91C_US_PAR_MARK [expr 0x3 << 9 ]
set AT91C_US_PAR_NONE [expr 0x4 << 9 ]
set AT91C_US_PAR_MULTI_DROP [expr 0x6 << 9 ]
set AT91C_US_NBSTOP [expr 0x3 << 12 ]
set AT91C_US_NBSTOP_1_BIT [expr 0x0 << 12 ]
set AT91C_US_NBSTOP_15_BIT [expr 0x1 << 12 ]
set AT91C_US_NBSTOP_2_BIT [expr 0x2 << 12 ]
set AT91C_US_CHMODE [expr 0x3 << 14 ]
set AT91C_US_CHMODE_NORMAL [expr 0x0 << 14 ]
set AT91C_US_CHMODE_AUTO [expr 0x1 << 14 ]
set AT91C_US_CHMODE_LOCAL [expr 0x2 << 14 ]
set AT91C_US_CHMODE_REMOTE [expr 0x3 << 14 ]
set AT91C_US_MSBF [expr 0x1 << 16 ]
set AT91C_US_MODE9 [expr 0x1 << 17 ]
set AT91C_US_CKLO [expr 0x1 << 18 ]
set AT91C_US_OVER [expr 0x1 << 19 ]
set AT91C_US_INACK [expr 0x1 << 20 ]
set AT91C_US_DSNACK [expr 0x1 << 21 ]
set AT91C_US_MAX_ITER [expr 0x1 << 24 ]
set AT91C_US_FILTER [expr 0x1 << 28 ]
# -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_RXBRK [expr 0x1 << 2 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TIMEOUT [expr 0x1 << 8 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_ITERATION [expr 0x1 << 10 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_NACK [expr 0x1 << 13 ]
set AT91C_US_RIIC [expr 0x1 << 16 ]
set AT91C_US_DSRIC [expr 0x1 << 17 ]
set AT91C_US_DCDIC [expr 0x1 << 18 ]
set AT91C_US_CTSIC [expr 0x1 << 19 ]
# -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_RXBRK [expr 0x1 << 2 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TIMEOUT [expr 0x1 << 8 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_ITERATION [expr 0x1 << 10 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_NACK [expr 0x1 << 13 ]
set AT91C_US_RIIC [expr 0x1 << 16 ]
set AT91C_US_DSRIC [expr 0x1 << 17 ]
set AT91C_US_DCDIC [expr 0x1 << 18 ]
set AT91C_US_CTSIC [expr 0x1 << 19 ]
# -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_RXBRK [expr 0x1 << 2 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TIMEOUT [expr 0x1 << 8 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_ITERATION [expr 0x1 << 10 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_NACK [expr 0x1 << 13 ]
set AT91C_US_RIIC [expr 0x1 << 16 ]
set AT91C_US_DSRIC [expr 0x1 << 17 ]
set AT91C_US_DCDIC [expr 0x1 << 18 ]
set AT91C_US_CTSIC [expr 0x1 << 19 ]
# -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
set AT91C_US_RXRDY [expr 0x1 << 0 ]
set AT91C_US_TXRDY [expr 0x1 << 1 ]
set AT91C_US_RXBRK [expr 0x1 << 2 ]
set AT91C_US_ENDRX [expr 0x1 << 3 ]
set AT91C_US_ENDTX [expr 0x1 << 4 ]
set AT91C_US_OVRE [expr 0x1 << 5 ]
set AT91C_US_FRAME [expr 0x1 << 6 ]
set AT91C_US_PARE [expr 0x1 << 7 ]
set AT91C_US_TIMEOUT [expr 0x1 << 8 ]
set AT91C_US_TXEMPTY [expr 0x1 << 9 ]
set AT91C_US_ITERATION [expr 0x1 << 10 ]
set AT91C_US_TXBUFE [expr 0x1 << 11 ]
set AT91C_US_RXBUFF [expr 0x1 << 12 ]
set AT91C_US_NACK [expr 0x1 << 13 ]
set AT91C_US_RIIC [expr 0x1 << 16 ]
set AT91C_US_DSRIC [expr 0x1 << 17 ]
set AT91C_US_DCDIC [expr 0x1 << 18 ]
set AT91C_US_CTSIC [expr 0x1 << 19 ]
set AT91C_US_RI [expr 0x1 << 20 ]
set AT91C_US_DSR [expr 0x1 << 21 ]
set AT91C_US_DCD [expr 0x1 << 22 ]
set AT91C_US_CTS [expr 0x1 << 23 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
# *****************************************************************************
# -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
set AT91C_SSC_RXEN [expr 0x1 << 0 ]
set AT91C_SSC_RXDIS [expr 0x1 << 1 ]
set AT91C_SSC_TXEN [expr 0x1 << 8 ]
set AT91C_SSC_TXDIS [expr 0x1 << 9 ]
set AT91C_SSC_SWRST [expr 0x1 << 15 ]
# -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
set AT91C_SSC_CKS [expr 0x3 << 0 ]
set AT91C_SSC_CKS_DIV 0x0
set AT91C_SSC_CKS_TK 0x1
set AT91C_SSC_CKS_RK 0x2
set AT91C_SSC_CKO [expr 0x7 << 2 ]
set AT91C_SSC_CKO_NONE [expr 0x0 << 2 ]
set AT91C_SSC_CKO_CONTINOUS [expr 0x1 << 2 ]
set AT91C_SSC_CKO_DATA_TX [expr 0x2 << 2 ]
set AT91C_SSC_CKI [expr 0x1 << 5 ]
set AT91C_SSC_CKG [expr 0x3 << 6 ]
set AT91C_SSC_CKG_NONE [expr 0x0 << 6 ]
set AT91C_SSC_CKG_LOW [expr 0x1 << 6 ]
set AT91C_SSC_CKG_HIGH [expr 0x2 << 6 ]
set AT91C_SSC_START [expr 0xF << 8 ]
set AT91C_SSC_START_CONTINOUS [expr 0x0 << 8 ]
set AT91C_SSC_START_TX [expr 0x1 << 8 ]
set AT91C_SSC_START_LOW_RF [expr 0x2 << 8 ]
set AT91C_SSC_START_HIGH_RF [expr 0x3 << 8 ]
set AT91C_SSC_START_FALL_RF [expr 0x4 << 8 ]
set AT91C_SSC_START_RISE_RF [expr 0x5 << 8 ]
set AT91C_SSC_START_LEVEL_RF [expr 0x6 << 8 ]
set AT91C_SSC_START_EDGE_RF [expr 0x7 << 8 ]
set AT91C_SSC_START_0 [expr 0x8 << 8 ]
set AT91C_SSC_STOP [expr 0x1 << 12 ]
set AT91C_SSC_STTDLY [expr 0xFF << 16 ]
set AT91C_SSC_PERIOD [expr 0xFF << 24 ]
# -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
set AT91C_SSC_DATLEN [expr 0x1F << 0 ]
set AT91C_SSC_LOOP [expr 0x1 << 5 ]
set AT91C_SSC_MSBF [expr 0x1 << 7 ]
set AT91C_SSC_DATNB [expr 0xF << 8 ]
set AT91C_SSC_FSLEN [expr 0xF << 16 ]
set AT91C_SSC_FSOS [expr 0x7 << 20 ]
set AT91C_SSC_FSOS_NONE [expr 0x0 << 20 ]
set AT91C_SSC_FSOS_NEGATIVE [expr 0x1 << 20 ]
set AT91C_SSC_FSOS_POSITIVE [expr 0x2 << 20 ]
set AT91C_SSC_FSOS_LOW [expr 0x3 << 20 ]
set AT91C_SSC_FSOS_HIGH [expr 0x4 << 20 ]
set AT91C_SSC_FSOS_TOGGLE [expr 0x5 << 20 ]
set AT91C_SSC_FSEDGE [expr 0x1 << 24 ]
# -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
set AT91C_SSC_CKS [expr 0x3 << 0 ]
set AT91C_SSC_CKS_DIV 0x0
set AT91C_SSC_CKS_TK 0x1
set AT91C_SSC_CKS_RK 0x2
set AT91C_SSC_CKO [expr 0x7 << 2 ]
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