?? at91sam7x256.tcl
字號(hào):
set AT91C_SSC_CKO_NONE [expr 0x0 << 2 ]
set AT91C_SSC_CKO_CONTINOUS [expr 0x1 << 2 ]
set AT91C_SSC_CKO_DATA_TX [expr 0x2 << 2 ]
set AT91C_SSC_CKI [expr 0x1 << 5 ]
set AT91C_SSC_CKG [expr 0x3 << 6 ]
set AT91C_SSC_CKG_NONE [expr 0x0 << 6 ]
set AT91C_SSC_CKG_LOW [expr 0x1 << 6 ]
set AT91C_SSC_CKG_HIGH [expr 0x2 << 6 ]
set AT91C_SSC_START [expr 0xF << 8 ]
set AT91C_SSC_START_CONTINOUS [expr 0x0 << 8 ]
set AT91C_SSC_START_TX [expr 0x1 << 8 ]
set AT91C_SSC_START_LOW_RF [expr 0x2 << 8 ]
set AT91C_SSC_START_HIGH_RF [expr 0x3 << 8 ]
set AT91C_SSC_START_FALL_RF [expr 0x4 << 8 ]
set AT91C_SSC_START_RISE_RF [expr 0x5 << 8 ]
set AT91C_SSC_START_LEVEL_RF [expr 0x6 << 8 ]
set AT91C_SSC_START_EDGE_RF [expr 0x7 << 8 ]
set AT91C_SSC_START_0 [expr 0x8 << 8 ]
set AT91C_SSC_STTDLY [expr 0xFF << 16 ]
set AT91C_SSC_PERIOD [expr 0xFF << 24 ]
# -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
set AT91C_SSC_DATLEN [expr 0x1F << 0 ]
set AT91C_SSC_DATDEF [expr 0x1 << 5 ]
set AT91C_SSC_MSBF [expr 0x1 << 7 ]
set AT91C_SSC_DATNB [expr 0xF << 8 ]
set AT91C_SSC_FSLEN [expr 0xF << 16 ]
set AT91C_SSC_FSOS [expr 0x7 << 20 ]
set AT91C_SSC_FSOS_NONE [expr 0x0 << 20 ]
set AT91C_SSC_FSOS_NEGATIVE [expr 0x1 << 20 ]
set AT91C_SSC_FSOS_POSITIVE [expr 0x2 << 20 ]
set AT91C_SSC_FSOS_LOW [expr 0x3 << 20 ]
set AT91C_SSC_FSOS_HIGH [expr 0x4 << 20 ]
set AT91C_SSC_FSOS_TOGGLE [expr 0x5 << 20 ]
set AT91C_SSC_FSDEN [expr 0x1 << 23 ]
set AT91C_SSC_FSEDGE [expr 0x1 << 24 ]
# -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
set AT91C_SSC_TXRDY [expr 0x1 << 0 ]
set AT91C_SSC_TXEMPTY [expr 0x1 << 1 ]
set AT91C_SSC_ENDTX [expr 0x1 << 2 ]
set AT91C_SSC_TXBUFE [expr 0x1 << 3 ]
set AT91C_SSC_RXRDY [expr 0x1 << 4 ]
set AT91C_SSC_OVRUN [expr 0x1 << 5 ]
set AT91C_SSC_ENDRX [expr 0x1 << 6 ]
set AT91C_SSC_RXBUFF [expr 0x1 << 7 ]
set AT91C_SSC_CP0 [expr 0x1 << 8 ]
set AT91C_SSC_CP1 [expr 0x1 << 9 ]
set AT91C_SSC_TXSYN [expr 0x1 << 10 ]
set AT91C_SSC_RXSYN [expr 0x1 << 11 ]
set AT91C_SSC_TXENA [expr 0x1 << 16 ]
set AT91C_SSC_RXENA [expr 0x1 << 17 ]
# -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
set AT91C_SSC_TXRDY [expr 0x1 << 0 ]
set AT91C_SSC_TXEMPTY [expr 0x1 << 1 ]
set AT91C_SSC_ENDTX [expr 0x1 << 2 ]
set AT91C_SSC_TXBUFE [expr 0x1 << 3 ]
set AT91C_SSC_RXRDY [expr 0x1 << 4 ]
set AT91C_SSC_OVRUN [expr 0x1 << 5 ]
set AT91C_SSC_ENDRX [expr 0x1 << 6 ]
set AT91C_SSC_RXBUFF [expr 0x1 << 7 ]
set AT91C_SSC_CP0 [expr 0x1 << 8 ]
set AT91C_SSC_CP1 [expr 0x1 << 9 ]
set AT91C_SSC_TXSYN [expr 0x1 << 10 ]
set AT91C_SSC_RXSYN [expr 0x1 << 11 ]
# -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
set AT91C_SSC_TXRDY [expr 0x1 << 0 ]
set AT91C_SSC_TXEMPTY [expr 0x1 << 1 ]
set AT91C_SSC_ENDTX [expr 0x1 << 2 ]
set AT91C_SSC_TXBUFE [expr 0x1 << 3 ]
set AT91C_SSC_RXRDY [expr 0x1 << 4 ]
set AT91C_SSC_OVRUN [expr 0x1 << 5 ]
set AT91C_SSC_ENDRX [expr 0x1 << 6 ]
set AT91C_SSC_RXBUFF [expr 0x1 << 7 ]
set AT91C_SSC_CP0 [expr 0x1 << 8 ]
set AT91C_SSC_CP1 [expr 0x1 << 9 ]
set AT91C_SSC_TXSYN [expr 0x1 << 10 ]
set AT91C_SSC_RXSYN [expr 0x1 << 11 ]
# -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
set AT91C_SSC_TXRDY [expr 0x1 << 0 ]
set AT91C_SSC_TXEMPTY [expr 0x1 << 1 ]
set AT91C_SSC_ENDTX [expr 0x1 << 2 ]
set AT91C_SSC_TXBUFE [expr 0x1 << 3 ]
set AT91C_SSC_RXRDY [expr 0x1 << 4 ]
set AT91C_SSC_OVRUN [expr 0x1 << 5 ]
set AT91C_SSC_ENDRX [expr 0x1 << 6 ]
set AT91C_SSC_RXBUFF [expr 0x1 << 7 ]
set AT91C_SSC_CP0 [expr 0x1 << 8 ]
set AT91C_SSC_CP1 [expr 0x1 << 9 ]
set AT91C_SSC_TXSYN [expr 0x1 << 10 ]
set AT91C_SSC_RXSYN [expr 0x1 << 11 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Two-wire Interface
# *****************************************************************************
# -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
set AT91C_TWI_START [expr 0x1 << 0 ]
set AT91C_TWI_STOP [expr 0x1 << 1 ]
set AT91C_TWI_MSEN [expr 0x1 << 2 ]
set AT91C_TWI_MSDIS [expr 0x1 << 3 ]
set AT91C_TWI_SWRST [expr 0x1 << 7 ]
# -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
set AT91C_TWI_IADRSZ [expr 0x3 << 8 ]
set AT91C_TWI_IADRSZ_NO [expr 0x0 << 8 ]
set AT91C_TWI_IADRSZ_1_BYTE [expr 0x1 << 8 ]
set AT91C_TWI_IADRSZ_2_BYTE [expr 0x2 << 8 ]
set AT91C_TWI_IADRSZ_3_BYTE [expr 0x3 << 8 ]
set AT91C_TWI_MREAD [expr 0x1 << 12 ]
set AT91C_TWI_DADR [expr 0x7F << 16 ]
# -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
set AT91C_TWI_CLDIV [expr 0xFF << 0 ]
set AT91C_TWI_CHDIV [expr 0xFF << 8 ]
set AT91C_TWI_CKDIV [expr 0x7 << 16 ]
# -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
set AT91C_TWI_TXCOMP [expr 0x1 << 0 ]
set AT91C_TWI_RXRDY [expr 0x1 << 1 ]
set AT91C_TWI_TXRDY [expr 0x1 << 2 ]
set AT91C_TWI_OVRE [expr 0x1 << 6 ]
set AT91C_TWI_UNRE [expr 0x1 << 7 ]
set AT91C_TWI_NACK [expr 0x1 << 8 ]
# -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
set AT91C_TWI_TXCOMP [expr 0x1 << 0 ]
set AT91C_TWI_RXRDY [expr 0x1 << 1 ]
set AT91C_TWI_TXRDY [expr 0x1 << 2 ]
set AT91C_TWI_OVRE [expr 0x1 << 6 ]
set AT91C_TWI_UNRE [expr 0x1 << 7 ]
set AT91C_TWI_NACK [expr 0x1 << 8 ]
# -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
set AT91C_TWI_TXCOMP [expr 0x1 << 0 ]
set AT91C_TWI_RXRDY [expr 0x1 << 1 ]
set AT91C_TWI_TXRDY [expr 0x1 << 2 ]
set AT91C_TWI_OVRE [expr 0x1 << 6 ]
set AT91C_TWI_UNRE [expr 0x1 << 7 ]
set AT91C_TWI_NACK [expr 0x1 << 8 ]
# -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
set AT91C_TWI_TXCOMP [expr 0x1 << 0 ]
set AT91C_TWI_RXRDY [expr 0x1 << 1 ]
set AT91C_TWI_TXRDY [expr 0x1 << 2 ]
set AT91C_TWI_OVRE [expr 0x1 << 6 ]
set AT91C_TWI_UNRE [expr 0x1 << 7 ]
set AT91C_TWI_NACK [expr 0x1 << 8 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR PWMC Channel Interface
# *****************************************************************************
# -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
set AT91C_PWMC_CPRE [expr 0xF << 0 ]
set AT91C_PWMC_CPRE_MCK 0x0
set AT91C_PWMC_CPRE_MCK/2 0x1
set AT91C_PWMC_CPRE_MCK/4 0x2
set AT91C_PWMC_CPRE_MCK/8 0x3
set AT91C_PWMC_CPRE_MCK/16 0x4
set AT91C_PWMC_CPRE_MCK/32 0x5
set AT91C_PWMC_CPRE_MCK/64 0x6
set AT91C_PWMC_CPRE_MCK/128 0x7
set AT91C_PWMC_CPRE_MCK/256 0x8
set AT91C_PWMC_CPRE_MCK/512 0x9
set AT91C_PWMC_CPRE_MCK/1024 0xA
set AT91C_PWMC_CPRE_MCKA 0xB
set AT91C_PWMC_CPRE_MCKB 0xC
set AT91C_PWMC_CALG [expr 0x1 << 8 ]
set AT91C_PWMC_CPOL [expr 0x1 << 9 ]
set AT91C_PWMC_CPD [expr 0x1 << 10 ]
# -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
set AT91C_PWMC_CDTY [expr 0x0 << 0 ]
# -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
set AT91C_PWMC_CPRD [expr 0x0 << 0 ]
# -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
set AT91C_PWMC_CCNT [expr 0x0 << 0 ]
# -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
set AT91C_PWMC_CUPD [expr 0x0 << 0 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
# *****************************************************************************
# -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
set AT91C_PWMC_DIVA [expr 0xFF << 0 ]
set AT91C_PWMC_PREA [expr 0xF << 8 ]
set AT91C_PWMC_PREA_MCK [expr 0x0 << 8 ]
set AT91C_PWMC_PREA_MCK/2 [expr 0x1 << 8 ]
set AT91C_PWMC_PREA_MCK/4 [expr 0x2 << 8 ]
set AT91C_PWMC_PREA_MCK/8 [expr 0x3 << 8 ]
set AT91C_PWMC_PREA_MCK/16 [expr 0x4 << 8 ]
set AT91C_PWMC_PREA_MCK/32 [expr 0x5 << 8 ]
set AT91C_PWMC_PREA_MCK/64 [expr 0x6 << 8 ]
set AT91C_PWMC_PREA_MCK/128 [expr 0x7 << 8 ]
set AT91C_PWMC_PREA_MCK/256 [expr 0x8 << 8 ]
set AT91C_PWMC_DIVB [expr 0xFF << 16 ]
set AT91C_PWMC_PREB [expr 0xF << 24 ]
set AT91C_PWMC_PREB_MCK [expr 0x0 << 24 ]
set AT91C_PWMC_PREB_MCK/2 [expr 0x1 << 24 ]
set AT91C_PWMC_PREB_MCK/4 [expr 0x2 << 24 ]
set AT91C_PWMC_PREB_MCK/8 [expr 0x3 << 24 ]
set AT91C_PWMC_PREB_MCK/16 [expr 0x4 << 24 ]
set AT91C_PWMC_PREB_MCK/32 [expr 0x5 << 24 ]
set AT91C_PWMC_PREB_MCK/64 [expr 0x6 << 24 ]
set AT91C_PWMC_PREB_MCK/128 [expr 0x7 << 24 ]
set AT91C_PWMC_PREB_MCK/256 [expr 0x8 << 24 ]
# -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
set AT91C_PWMC_CHID0 [expr 0x1 << 0 ]
set AT91C_PWMC_CHID1 [expr 0x1 << 1 ]
set AT91C_PWMC_CHID2 [expr 0x1 << 2 ]
set AT91C_PWMC_CHID3 [expr 0x1 << 3 ]
# *****************************************************************************
# SOFTWARE API DEFINITION FOR USB Device Interface
# *****************************************************************************
# -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
set AT91C_UDP_FRM_NUM [expr 0x7FF << 0 ]
set AT91C_UDP_FRM_ERR [expr 0x1 << 16 ]
set AT91C_UDP_FRM_OK [expr 0x1 << 17 ]
# -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
set AT91C_UDP_FADDEN [expr 0x1 << 0 ]
set AT91C_UDP_CONFG [expr 0x1 << 1 ]
set AT91C_UDP_ESR [expr 0x1 << 2 ]
set AT91C_UDP_RSMINPR [expr 0x1 << 3 ]
set AT91C_UDP_RMWUPE [expr 0x1 << 4 ]
# -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
set AT91C_UDP_FADD [expr 0xFF << 0 ]
set AT91C_UDP_FEN [expr 0x1 << 8 ]
# -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
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