/*
 *  SPI function.
 *
 * This file contains the definitions for SPI port.
 *
 *  Author: flpan 
 *  Copyright (C) 2000 by UTStarcom, Inc.
 *
 *
 *  $Id: spi.h,v 1.4 2002/07/31 17:20:58 suvrat Exp $
 */
#ifndef __SPI_H
#define __SPI_H

#include <rtems.h>
/*#include "drvcomn.h"*/

#define SPI_MINOR        6
#define SPI_DEBUG
#define FPGA_FILE_NAME    "/flash/fpga1.bin"

/* /CS and I/O signals definition */
/* PB27 used as /EEPROM_CS output */
#define SPI_EEPROM_CS       (1 << 4)

/* PD18 used as SPI_CLK */
#define SPI_CLK       (1 << (31 - 18))

/* PD17 used as SPI_OUTPUT */
#define SPI_OUTPUT    (1 << (31 - 17))

/* PD16 used as SPI_INPUT */
#define SPI_INPUT     (1 << (31 - 16))

/* PB30 used as FPGA_INIT input */
#define FPGA_INIT        (1 << 1)
/* PB29 used as FPGA_DONE input */
#define FPGA_DONE        (1 << 2)

/* PB31 used as /FPGA_PROGRAM output */
#define FPGA_PROGRAM     1

/* PB25 used as /EEPROMWP output */
#define SPI_EEPROM_WP       (1 << 6)
/* PB26 used as /EEPROMHOLD output */
#define SPI_EEPROM_HOLD     (1 << 5)

#if CPM_166
/* SPI_CLK is 1M when BRGCLK is 83M (166M * 2 / 4), LSB first */
#define SPI_NORMAL_MODE  0x0A71
#else
/* SPI_CLK is 1M when BRGCLK is 83M (133 * 2 / 4), LSB first */
#define SPI_NORMAL_MODE  0x0A70
#endif

#if CPM_166
/* SPI_CLK is 1M when BRGCLK is 83M */
#define SPI_FAST_MODE    0x0EF1
#else
/* SPI_CLK is 1M when BRGCLK is 66.5 */
#define SPI_FAST_MODE    0x0EF0
#endif

#if CPM_166
/* SPI_CLK is ~2.1MHz, clock starts toggling at middle of xfer */
#define SPI_EEPROM_MODE     0x0679
#else
#define SPI_EEPROM_MODE     0x0677
#endif
#define SPI_PAGE_SIZE	 	512	

/* FPGA read/write command opcode */
#define FPGA_WRITE_CMD   0x02
#define FPGA_READ_CMD    0x03

#define SPI_SUCCESSFUL   0
#define SPI_FAILURE      1

/* Define SPI device driver major and minor value */
#define SPI_MAJOR_NUMBER 0
#define SPI_MINOR_NUMBER 6

typedef enum {
  SPI_READ_FPGA_REG = 0,
  SPI_WRITE_FPGA_REG,
  SPI_CONFIG_FPGA,
  SPI_EEPROM_XFER
} spi_opcode_e;

/* The C structure that is used in the ioctl operations */
typedef struct {
  U32 fpga_num;   /* The FPGA from which the register has to be read/write */
  U32 reg_num;    /* For read/write it specifies te register */
  U32 reg_data;   /* For read/write will have the data */
} spi_reg_parm_t;

typedef struct {
  spi_opcode_e opcode;
  void *data_p;
} spi_ctrl_t;

/* EEPROM structures */
typedef struct {
  U16 length;     /* Length of the block read/write - includes address byte */
  U8  *tx_p;      /* Transmit buffer */
  U8  *rx_p;      /* Receive buffer */
} spi_eeprom_parm_t;

/* prototype */
void m8260_spi_start();
void m8260_spi_fast_mode();
void m8260_spi_normal_mode();
void m8260_spi_loop_normal();
void m8260_spi_loop_back();
void m8260_spi_eeprom_mode(U16 mrbl);
rtems_status_code spi_initialize (rtems_device_major_number major,
																	rtems_device_minor_number minor,
																	void *arg_p);
rtems_status_code spi_read(void *arg_p);
rtems_status_code spi_write(void *arg_p);
rtems_status_code fpga_configure();
rtems_status_code spi_control(rtems_device_major_number major,
                              rtems_device_minor_number minor,
															void *arg_p);
rtems_status_code spi_eeprom_xfer(void *arg_p);

#endif