//------------------------------------------------------------------------------
// <copyright file="mc_reg.h" company="Atheros">
//    Copyright (c) 2006 Microsoft Corporation.  All rights reserved.
//    Copyright (c) 2006 Atheros Corporation.  All rights reserved.
//
//    The use and distribution terms for this software are covered by the
//    Microsoft Limited Permissive License (Ms-LPL) 
//    http://www.microsoft.com/resources/sharedsource/licensingbasics/limitedpermissivelicense.mspx 
//    which can be found in the file MS-LPL.txt at the root of this distribution.
//    By using this software in any fashion, you are agreeing to be bound by
//    the terms of this license.
//
//    You must not remove this notice, or any other, from this software.
// </copyright>
// 
// <summary>
//    Windows CE Wifi Driver for AR-6000
// </summary>
//------------------------------------------------------------------------------
//==============================================================================
// MC registers definition
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _MC_REG_H_
#define _MC_REG_H_

#define BANK0_ADDR_ADDRESS                       0x0c004000
#define BANK0_ADDR_OFFSET                        0x00000000
#define BANK0_ADDR_SIZE_MSB                      31
#define BANK0_ADDR_SIZE_LSB                      28
#define BANK0_ADDR_SIZE_MASK                     0xf0000000
#define BANK0_ADDR_SIZE_GET(x)                   (((x) & BANK0_ADDR_SIZE_MASK) >> BANK0_ADDR_SIZE_LSB)
#define BANK0_ADDR_SIZE_SET(x)                   (((x) << BANK0_ADDR_SIZE_LSB) & BANK0_ADDR_SIZE_MASK)
#define BANK0_ADDR_BASE_MSB                      27
#define BANK0_ADDR_BASE_LSB                      10
#define BANK0_ADDR_BASE_MASK                     0x0ffffc00
#define BANK0_ADDR_BASE_GET(x)                   (((x) & BANK0_ADDR_BASE_MASK) >> BANK0_ADDR_BASE_LSB)
#define BANK0_ADDR_BASE_SET(x)                   (((x) << BANK0_ADDR_BASE_LSB) & BANK0_ADDR_BASE_MASK)

#define BANK0_CONFIG_ADDRESS                     0x0c004004
#define BANK0_CONFIG_OFFSET                      0x00000004
#define BANK0_CONFIG_ENABLE_MSB                  31
#define BANK0_CONFIG_ENABLE_LSB                  31
#define BANK0_CONFIG_ENABLE_MASK                 0x80000000
#define BANK0_CONFIG_ENABLE_GET(x)               (((x) & BANK0_CONFIG_ENABLE_MASK) >> BANK0_CONFIG_ENABLE_LSB)
#define BANK0_CONFIG_ENABLE_SET(x)               (((x) << BANK0_CONFIG_ENABLE_LSB) & BANK0_CONFIG_ENABLE_MASK)
#define BANK0_CONFIG_WIDTH_MSB                   28
#define BANK0_CONFIG_WIDTH_LSB                   28
#define BANK0_CONFIG_WIDTH_MASK                  0x10000000
#define BANK0_CONFIG_WIDTH_GET(x)                (((x) & BANK0_CONFIG_WIDTH_MASK) >> BANK0_CONFIG_WIDTH_LSB)
#define BANK0_CONFIG_WIDTH_SET(x)                (((x) << BANK0_CONFIG_WIDTH_LSB) & BANK0_CONFIG_WIDTH_MASK)
#define BANK0_CONFIG_PROTECT_MSB                 26
#define BANK0_CONFIG_PROTECT_LSB                 26
#define BANK0_CONFIG_PROTECT_MASK                0x04000000
#define BANK0_CONFIG_PROTECT_GET(x)              (((x) & BANK0_CONFIG_PROTECT_MASK) >> BANK0_CONFIG_PROTECT_LSB)
#define BANK0_CONFIG_PROTECT_SET(x)              (((x) << BANK0_CONFIG_PROTECT_LSB) & BANK0_CONFIG_PROTECT_MASK)
#define BANK0_CONFIG_WB_ENABLE_MSB               25
#define BANK0_CONFIG_WB_ENABLE_LSB               25
#define BANK0_CONFIG_WB_ENABLE_MASK              0x02000000
#define BANK0_CONFIG_WB_ENABLE_GET(x)            (((x) & BANK0_CONFIG_WB_ENABLE_MASK) >> BANK0_CONFIG_WB_ENABLE_LSB)
#define BANK0_CONFIG_WB_ENABLE_SET(x)            (((x) << BANK0_CONFIG_WB_ENABLE_LSB) & BANK0_CONFIG_WB_ENABLE_MASK)
#define BANK0_CONFIG_WB_FLUSH_MSB                24
#define BANK0_CONFIG_WB_FLUSH_LSB                24
#define BANK0_CONFIG_WB_FLUSH_MASK               0x01000000
#define BANK0_CONFIG_WB_FLUSH_GET(x)             (((x) & BANK0_CONFIG_WB_FLUSH_MASK) >> BANK0_CONFIG_WB_FLUSH_LSB)
#define BANK0_CONFIG_WB_FLUSH_SET(x)             (((x) << BANK0_CONFIG_WB_FLUSH_LSB) & BANK0_CONFIG_WB_FLUSH_MASK)
#define BANK0_CONFIG_SCALE_MSB                   21
#define BANK0_CONFIG_SCALE_LSB                   20
#define BANK0_CONFIG_SCALE_MASK                  0x00300000
#define BANK0_CONFIG_SCALE_GET(x)                (((x) & BANK0_CONFIG_SCALE_MASK) >> BANK0_CONFIG_SCALE_LSB)
#define BANK0_CONFIG_SCALE_SET(x)                (((x) << BANK0_CONFIG_SCALE_LSB) & BANK0_CONFIG_SCALE_MASK)
#define BANK0_CONFIG_HOLDOFF_MSB                 19
#define BANK0_CONFIG_HOLDOFF_LSB                 16
#define BANK0_CONFIG_HOLDOFF_MASK                0x000f0000
#define BANK0_CONFIG_HOLDOFF_GET(x)              (((x) & BANK0_CONFIG_HOLDOFF_MASK) >> BANK0_CONFIG_HOLDOFF_LSB)
#define BANK0_CONFIG_HOLDOFF_SET(x)              (((x) << BANK0_CONFIG_HOLDOFF_LSB) & BANK0_CONFIG_HOLDOFF_MASK)
#define BANK0_CONFIG_TIMER3_MSB                  15
#define BANK0_CONFIG_TIMER3_LSB                  12
#define BANK0_CONFIG_TIMER3_MASK                 0x0000f000
#define BANK0_CONFIG_TIMER3_GET(x)               (((x) & BANK0_CONFIG_TIMER3_MASK) >> BANK0_CONFIG_TIMER3_LSB)
#define BANK0_CONFIG_TIMER3_SET(x)               (((x) << BANK0_CONFIG_TIMER3_LSB) & BANK0_CONFIG_TIMER3_MASK)
#define BANK0_CONFIG_TIMER2_MSB                  11
#define BANK0_CONFIG_TIMER2_LSB                  8
#define BANK0_CONFIG_TIMER2_MASK                 0x00000f00
#define BANK0_CONFIG_TIMER2_GET(x)               (((x) & BANK0_CONFIG_TIMER2_MASK) >> BANK0_CONFIG_TIMER2_LSB)
#define BANK0_CONFIG_TIMER2_SET(x)               (((x) << BANK0_CONFIG_TIMER2_LSB) & BANK0_CONFIG_TIMER2_MASK)
#define BANK0_CONFIG_TIMER1_MSB                  7
#define BANK0_CONFIG_TIMER1_LSB                  4
#define BANK0_CONFIG_TIMER1_MASK                 0x000000f0
#define BANK0_CONFIG_TIMER1_GET(x)               (((x) & BANK0_CONFIG_TIMER1_MASK) >> BANK0_CONFIG_TIMER1_LSB)
#define BANK0_CONFIG_TIMER1_SET(x)               (((x) << BANK0_CONFIG_TIMER1_LSB) & BANK0_CONFIG_TIMER1_MASK)
#define BANK0_CONFIG_TIMER0_MSB                  3
#define BANK0_CONFIG_TIMER0_LSB                  0
#define BANK0_CONFIG_TIMER0_MASK                 0x0000000f
#define BANK0_CONFIG_TIMER0_GET(x)               (((x) & BANK0_CONFIG_TIMER0_MASK) >> BANK0_CONFIG_TIMER0_LSB)
#define BANK0_CONFIG_TIMER0_SET(x)               (((x) << BANK0_CONFIG_TIMER0_LSB) & BANK0_CONFIG_TIMER0_MASK)

#define BANK0_READ_ADDRESS                       0x0c004008
#define BANK0_READ_OFFSET                        0x00000008
#define BANK0_READ_ENABLE_WAIT_MSB               31
#define BANK0_READ_ENABLE_WAIT_LSB               31
#define BANK0_READ_ENABLE_WAIT_MASK              0x80000000
#define BANK0_READ_ENABLE_WAIT_GET(x)            (((x) & BANK0_READ_ENABLE_WAIT_MASK) >> BANK0_READ_ENABLE_WAIT_LSB)
#define BANK0_READ_ENABLE_WAIT_SET(x)            (((x) << BANK0_READ_ENABLE_WAIT_LSB) & BANK0_READ_ENABLE_WAIT_MASK)
#define BANK0_READ_WAIT_EVENT_MSB                30
#define BANK0_READ_WAIT_EVENT_LSB                28
#define BANK0_READ_WAIT_EVENT_MASK               0x70000000
#define BANK0_READ_WAIT_EVENT_GET(x)             (((x) & BANK0_READ_WAIT_EVENT_MASK) >> BANK0_READ_WAIT_EVENT_LSB)
#define BANK0_READ_WAIT_EVENT_SET(x)             (((x) << BANK0_READ_WAIT_EVENT_LSB) & BANK0_READ_WAIT_EVENT_MASK)
#define BANK0_READ_END_EVENT_MSB                 26
#define BANK0_READ_END_EVENT_LSB                 24
#define BANK0_READ_END_EVENT_MASK                0x07000000
#define BANK0_READ_END_EVENT_GET(x)              (((x) & BANK0_READ_END_EVENT_MASK) >> BANK0_READ_END_EVENT_LSB)
#define BANK0_READ_END_EVENT_SET(x)              (((x) << BANK0_READ_END_EVENT_LSB) & BANK0_READ_END_EVENT_MASK)
#define BANK0_READ_BURST_END_EVENT_MSB           22
#define BANK0_READ_BURST_END_EVENT_LSB           20
#define BANK0_READ_BURST_END_EVENT_MASK          0x00700000
#define BANK0_READ_BURST_END_EVENT_GET(x)        (((x) & BANK0_READ_BURST_END_EVENT_MASK) >> BANK0_READ_BURST_END_EVENT_LSB)
#define BANK0_READ_BURST_END_EVENT_SET(x)        (((x) << BANK0_READ_BURST_END_EVENT_LSB) & BANK0_READ_BURST_END_EVENT_MASK)
#define BANK0_READ_BURST_START_EVENT_MSB         18
#define BANK0_READ_BURST_START_EVENT_LSB         16
#define BANK0_READ_BURST_START_EVENT_MASK        0x00070000
#define BANK0_READ_BURST_START_EVENT_GET(x)      (((x) & BANK0_READ_BURST_START_EVENT_MASK) >> BANK0_READ_BURST_START_EVENT_LSB)
#define BANK0_READ_BURST_START_EVENT_SET(x)      (((x) << BANK0_READ_BURST_START_EVENT_LSB) & BANK0_READ_BURST_START_EVENT_MASK)
#define BANK0_READ_EVENT3_DC_MSB                 15
#define BANK0_READ_EVENT3_DC_LSB                 15
#define BANK0_READ_EVENT3_DC_MASK                0x00008000
#define BANK0_READ_EVENT3_DC_GET(x)              (((x) & BANK0_READ_EVENT3_DC_MASK) >> BANK0_READ_EVENT3_DC_LSB)
#define BANK0_READ_EVENT3_DC_SET(x)              (((x) << BANK0_READ_EVENT3_DC_LSB) & BANK0_READ_EVENT3_DC_MASK)
#define BANK0_READ_EVENT3_BE_MSB                 14
#define BANK0_READ_EVENT3_BE_LSB                 14
#define BANK0_READ_EVENT3_BE_MASK                0x00004000
#define BANK0_READ_EVENT3_BE_GET(x)              (((x) & BANK0_READ_EVENT3_BE_MASK) >> BANK0_READ_EVENT3_BE_LSB)
#define BANK0_READ_EVENT3_BE_SET(x)              (((x) << BANK0_READ_EVENT3_BE_LSB) & BANK0_READ_EVENT3_BE_MASK)
#define BANK0_READ_EVENT3_OE_MSB                 13
#define BANK0_READ_EVENT3_OE_LSB                 13
#define BANK0_READ_EVENT3_OE_MASK                0x00002000
#define BANK0_READ_EVENT3_OE_GET(x)              (((x) & BANK0_READ_EVENT3_OE_MASK) >> BANK0_READ_EVENT3_OE_LSB)
#define BANK0_READ_EVENT3_OE_SET(x)              (((x) << BANK0_READ_EVENT3_OE_LSB) & BANK0_READ_EVENT3_OE_MASK)
#define BANK0_READ_EVENT3_CS_MSB                 12
#define BANK0_READ_EVENT3_CS_LSB                 12
#define BANK0_READ_EVENT3_CS_MASK                0x00001000
#define BANK0_READ_EVENT3_CS_GET(x)              (((x) & BANK0_READ_EVENT3_CS_MASK) >> BANK0_READ_EVENT3_CS_LSB)
#define BANK0_READ_EVENT3_CS_SET(x)              (((x) << BANK0_READ_EVENT3_CS_LSB) & BANK0_READ_EVENT3_CS_MASK)
#define BANK0_READ_EVENT2_DC_MSB                 11
#define BANK0_READ_EVENT2_DC_LSB                 11
#define BANK0_READ_EVENT2_DC_MASK                0x00000800
#define BANK0_READ_EVENT2_DC_GET(x)              (((x) & BANK0_READ_EVENT2_DC_MASK) >> BANK0_READ_EVENT2_DC_LSB)
#define BANK0_READ_EVENT2_DC_SET(x)              (((x) << BANK0_READ_EVENT2_DC_LSB) & BANK0_READ_EVENT2_DC_MASK)
#define BANK0_READ_EVENT2_BE_MSB                 10
#define BANK0_READ_EVENT2_BE_LSB                 10
#define BANK0_READ_EVENT2_BE_MASK                0x00000400
#define BANK0_READ_EVENT2_BE_GET(x)              (((x) & BANK0_READ_EVENT2_BE_MASK) >> BANK0_READ_EVENT2_BE_LSB)
#define BANK0_READ_EVENT2_BE_SET(x)              (((x) << BANK0_READ_EVENT2_BE_LSB) & BANK0_READ_EVENT2_BE_MASK)
#define BANK0_READ_EVENT2_OE_MSB                 9
#define BANK0_READ_EVENT2_OE_LSB                 9
#define BANK0_READ_EVENT2_OE_MASK                0x00000200
#define BANK0_READ_EVENT2_OE_GET(x)              (((x) & BANK0_READ_EVENT2_OE_MASK) >> BANK0_READ_EVENT2_OE_LSB)
#define BANK0_READ_EVENT2_OE_SET(x)              (((x) << BANK0_READ_EVENT2_OE_LSB) & BANK0_READ_EVENT2_OE_MASK)
#define BANK0_READ_EVENT2_CS_MSB                 8
#define BANK0_READ_EVENT2_CS_LSB                 8
#define BANK0_READ_EVENT2_CS_MASK                0x00000100
#define BANK0_READ_EVENT2_CS_GET(x)              (((x) & BANK0_READ_EVENT2_CS_MASK) >> BANK0_READ_EVENT2_CS_LSB)
#define BANK0_READ_EVENT2_CS_SET(x)              (((x) << BANK0_READ_EVENT2_CS_LSB) & BANK0_READ_EVENT2_CS_MASK)
#define BANK0_READ_EVENT1_DC_MSB                 7
#define BANK0_READ_EVENT1_DC_LSB                 7
#define BANK0_READ_EVENT1_DC_MASK                0x00000080
#define BANK0_READ_EVENT1_DC_GET(x)              (((x) & BANK0_READ_EVENT1_DC_MASK) >> BANK0_READ_EVENT1_DC_LSB)
#define BANK0_READ_EVENT1_DC_SET(x)              (((x) << BANK0_READ_EVENT1_DC_LSB) & BANK0_READ_EVENT1_DC_MASK)
#define BANK0_READ_EVENT1_BE_MSB                 6
#define BANK0_READ_EVENT1_BE_LSB                 6
#define BANK0_READ_EVENT1_BE_MASK                0x00000040