#define BANK0_READ_EVENT1_BE_GET(x)              (((x) & BANK0_READ_EVENT1_BE_MASK) >> BANK0_READ_EVENT1_BE_LSB)
#define BANK0_READ_EVENT1_BE_SET(x)              (((x) << BANK0_READ_EVENT1_BE_LSB) & BANK0_READ_EVENT1_BE_MASK)
#define BANK0_READ_EVENT1_OE_MSB                 5
#define BANK0_READ_EVENT1_OE_LSB                 5
#define BANK0_READ_EVENT1_OE_MASK                0x00000020
#define BANK0_READ_EVENT1_OE_GET(x)              (((x) & BANK0_READ_EVENT1_OE_MASK) >> BANK0_READ_EVENT1_OE_LSB)
#define BANK0_READ_EVENT1_OE_SET(x)              (((x) << BANK0_READ_EVENT1_OE_LSB) & BANK0_READ_EVENT1_OE_MASK)
#define BANK0_READ_EVENT1_CS_MSB                 4
#define BANK0_READ_EVENT1_CS_LSB                 4
#define BANK0_READ_EVENT1_CS_MASK                0x00000010
#define BANK0_READ_EVENT1_CS_GET(x)              (((x) & BANK0_READ_EVENT1_CS_MASK) >> BANK0_READ_EVENT1_CS_LSB)
#define BANK0_READ_EVENT1_CS_SET(x)              (((x) << BANK0_READ_EVENT1_CS_LSB) & BANK0_READ_EVENT1_CS_MASK)
#define BANK0_READ_EVENT0_DC_MSB                 3
#define BANK0_READ_EVENT0_DC_LSB                 3
#define BANK0_READ_EVENT0_DC_MASK                0x00000008
#define BANK0_READ_EVENT0_DC_GET(x)              (((x) & BANK0_READ_EVENT0_DC_MASK) >> BANK0_READ_EVENT0_DC_LSB)
#define BANK0_READ_EVENT0_DC_SET(x)              (((x) << BANK0_READ_EVENT0_DC_LSB) & BANK0_READ_EVENT0_DC_MASK)
#define BANK0_READ_EVENT0_BE_MSB                 2
#define BANK0_READ_EVENT0_BE_LSB                 2
#define BANK0_READ_EVENT0_BE_MASK                0x00000004
#define BANK0_READ_EVENT0_BE_GET(x)              (((x) & BANK0_READ_EVENT0_BE_MASK) >> BANK0_READ_EVENT0_BE_LSB)
#define BANK0_READ_EVENT0_BE_SET(x)              (((x) << BANK0_READ_EVENT0_BE_LSB) & BANK0_READ_EVENT0_BE_MASK)
#define BANK0_READ_EVENT0_OE_MSB                 1
#define BANK0_READ_EVENT0_OE_LSB                 1
#define BANK0_READ_EVENT0_OE_MASK                0x00000002
#define BANK0_READ_EVENT0_OE_GET(x)              (((x) & BANK0_READ_EVENT0_OE_MASK) >> BANK0_READ_EVENT0_OE_LSB)
#define BANK0_READ_EVENT0_OE_SET(x)              (((x) << BANK0_READ_EVENT0_OE_LSB) & BANK0_READ_EVENT0_OE_MASK)
#define BANK0_READ_EVENT0_CS_MSB                 0
#define BANK0_READ_EVENT0_CS_LSB                 0
#define BANK0_READ_EVENT0_CS_MASK                0x00000001
#define BANK0_READ_EVENT0_CS_GET(x)              (((x) & BANK0_READ_EVENT0_CS_MASK) >> BANK0_READ_EVENT0_CS_LSB)
#define BANK0_READ_EVENT0_CS_SET(x)              (((x) << BANK0_READ_EVENT0_CS_LSB) & BANK0_READ_EVENT0_CS_MASK)

#define BANK0_WRITE_ADDRESS                      0x0c00400c
#define BANK0_WRITE_OFFSET                       0x0000000c
#define BANK0_WRITE_ENABLE_WAIT_MSB              31
#define BANK0_WRITE_ENABLE_WAIT_LSB              31
#define BANK0_WRITE_ENABLE_WAIT_MASK             0x80000000
#define BANK0_WRITE_ENABLE_WAIT_GET(x)           (((x) & BANK0_WRITE_ENABLE_WAIT_MASK) >> BANK0_WRITE_ENABLE_WAIT_LSB)
#define BANK0_WRITE_ENABLE_WAIT_SET(x)           (((x) << BANK0_WRITE_ENABLE_WAIT_LSB) & BANK0_WRITE_ENABLE_WAIT_MASK)
#define BANK0_WRITE_WAIT_EVENT_MSB               30
#define BANK0_WRITE_WAIT_EVENT_LSB               28
#define BANK0_WRITE_WAIT_EVENT_MASK              0x70000000
#define BANK0_WRITE_WAIT_EVENT_GET(x)            (((x) & BANK0_WRITE_WAIT_EVENT_MASK) >> BANK0_WRITE_WAIT_EVENT_LSB)
#define BANK0_WRITE_WAIT_EVENT_SET(x)            (((x) << BANK0_WRITE_WAIT_EVENT_LSB) & BANK0_WRITE_WAIT_EVENT_MASK)
#define BANK0_WRITE_END_EVENT_MSB                26
#define BANK0_WRITE_END_EVENT_LSB                24
#define BANK0_WRITE_END_EVENT_MASK               0x07000000
#define BANK0_WRITE_END_EVENT_GET(x)             (((x) & BANK0_WRITE_END_EVENT_MASK) >> BANK0_WRITE_END_EVENT_LSB)
#define BANK0_WRITE_END_EVENT_SET(x)             (((x) << BANK0_WRITE_END_EVENT_LSB) & BANK0_WRITE_END_EVENT_MASK)
#define BANK0_WRITE_BURST_END_EVENT_MSB          22
#define BANK0_WRITE_BURST_END_EVENT_LSB          20
#define BANK0_WRITE_BURST_END_EVENT_MASK         0x00700000
#define BANK0_WRITE_BURST_END_EVENT_GET(x)       (((x) & BANK0_WRITE_BURST_END_EVENT_MASK) >> BANK0_WRITE_BURST_END_EVENT_LSB)
#define BANK0_WRITE_BURST_END_EVENT_SET(x)       (((x) << BANK0_WRITE_BURST_END_EVENT_LSB) & BANK0_WRITE_BURST_END_EVENT_MASK)
#define BANK0_WRITE_BURST_START_EVENT_MSB        18
#define BANK0_WRITE_BURST_START_EVENT_LSB        16
#define BANK0_WRITE_BURST_START_EVENT_MASK       0x00070000
#define BANK0_WRITE_BURST_START_EVENT_GET(x)     (((x) & BANK0_WRITE_BURST_START_EVENT_MASK) >> BANK0_WRITE_BURST_START_EVENT_LSB)
#define BANK0_WRITE_BURST_START_EVENT_SET(x)     (((x) << BANK0_WRITE_BURST_START_EVENT_LSB) & BANK0_WRITE_BURST_START_EVENT_MASK)
#define BANK0_WRITE_EVENT3_BE_MSB                14
#define BANK0_WRITE_EVENT3_BE_LSB                14
#define BANK0_WRITE_EVENT3_BE_MASK               0x00004000
#define BANK0_WRITE_EVENT3_BE_GET(x)             (((x) & BANK0_WRITE_EVENT3_BE_MASK) >> BANK0_WRITE_EVENT3_BE_LSB)
#define BANK0_WRITE_EVENT3_BE_SET(x)             (((x) << BANK0_WRITE_EVENT3_BE_LSB) & BANK0_WRITE_EVENT3_BE_MASK)
#define BANK0_WRITE_EVENT3_WE_MSB                13
#define BANK0_WRITE_EVENT3_WE_LSB                13
#define BANK0_WRITE_EVENT3_WE_MASK               0x00002000
#define BANK0_WRITE_EVENT3_WE_GET(x)             (((x) & BANK0_WRITE_EVENT3_WE_MASK) >> BANK0_WRITE_EVENT3_WE_LSB)
#define BANK0_WRITE_EVENT3_WE_SET(x)             (((x) << BANK0_WRITE_EVENT3_WE_LSB) & BANK0_WRITE_EVENT3_WE_MASK)
#define BANK0_WRITE_EVENT3_CS_MSB                12
#define BANK0_WRITE_EVENT3_CS_LSB                12
#define BANK0_WRITE_EVENT3_CS_MASK               0x00001000
#define BANK0_WRITE_EVENT3_CS_GET(x)             (((x) & BANK0_WRITE_EVENT3_CS_MASK) >> BANK0_WRITE_EVENT3_CS_LSB)
#define BANK0_WRITE_EVENT3_CS_SET(x)             (((x) << BANK0_WRITE_EVENT3_CS_LSB) & BANK0_WRITE_EVENT3_CS_MASK)
#define BANK0_WRITE_EVENT2_BE_MSB                10
#define BANK0_WRITE_EVENT2_BE_LSB                10
#define BANK0_WRITE_EVENT2_BE_MASK               0x00000400
#define BANK0_WRITE_EVENT2_BE_GET(x)             (((x) & BANK0_WRITE_EVENT2_BE_MASK) >> BANK0_WRITE_EVENT2_BE_LSB)
#define BANK0_WRITE_EVENT2_BE_SET(x)             (((x) << BANK0_WRITE_EVENT2_BE_LSB) & BANK0_WRITE_EVENT2_BE_MASK)
#define BANK0_WRITE_EVENT2_WE_MSB                9
#define BANK0_WRITE_EVENT2_WE_LSB                9
#define BANK0_WRITE_EVENT2_WE_MASK               0x00000200
#define BANK0_WRITE_EVENT2_WE_GET(x)             (((x) & BANK0_WRITE_EVENT2_WE_MASK) >> BANK0_WRITE_EVENT2_WE_LSB)
#define BANK0_WRITE_EVENT2_WE_SET(x)             (((x) << BANK0_WRITE_EVENT2_WE_LSB) & BANK0_WRITE_EVENT2_WE_MASK)
#define BANK0_WRITE_EVENT2_CS_MSB                8
#define BANK0_WRITE_EVENT2_CS_LSB                8
#define BANK0_WRITE_EVENT2_CS_MASK               0x00000100
#define BANK0_WRITE_EVENT2_CS_GET(x)             (((x) & BANK0_WRITE_EVENT2_CS_MASK) >> BANK0_WRITE_EVENT2_CS_LSB)
#define BANK0_WRITE_EVENT2_CS_SET(x)             (((x) << BANK0_WRITE_EVENT2_CS_LSB) & BANK0_WRITE_EVENT2_CS_MASK)
#define BANK0_WRITE_EVENT1_BE_MSB                6
#define BANK0_WRITE_EVENT1_BE_LSB                6
#define BANK0_WRITE_EVENT1_BE_MASK               0x00000040
#define BANK0_WRITE_EVENT1_BE_GET(x)             (((x) & BANK0_WRITE_EVENT1_BE_MASK) >> BANK0_WRITE_EVENT1_BE_LSB)
#define BANK0_WRITE_EVENT1_BE_SET(x)             (((x) << BANK0_WRITE_EVENT1_BE_LSB) & BANK0_WRITE_EVENT1_BE_MASK)
#define BANK0_WRITE_EVENT1_WE_MSB                5
#define BANK0_WRITE_EVENT1_WE_LSB                5
#define BANK0_WRITE_EVENT1_WE_MASK               0x00000020
#define BANK0_WRITE_EVENT1_WE_GET(x)             (((x) & BANK0_WRITE_EVENT1_WE_MASK) >> BANK0_WRITE_EVENT1_WE_LSB)
#define BANK0_WRITE_EVENT1_WE_SET(x)             (((x) << BANK0_WRITE_EVENT1_WE_LSB) & BANK0_WRITE_EVENT1_WE_MASK)
#define BANK0_WRITE_EVENT1_CS_MSB                4
#define BANK0_WRITE_EVENT1_CS_LSB                4
#define BANK0_WRITE_EVENT1_CS_MASK               0x00000010
#define BANK0_WRITE_EVENT1_CS_GET(x)             (((x) & BANK0_WRITE_EVENT1_CS_MASK) >> BANK0_WRITE_EVENT1_CS_LSB)
#define BANK0_WRITE_EVENT1_CS_SET(x)             (((x) << BANK0_WRITE_EVENT1_CS_LSB) & BANK0_WRITE_EVENT1_CS_MASK)
#define BANK0_WRITE_EVENT0_BE_MSB                2
#define BANK0_WRITE_EVENT0_BE_LSB                2
#define BANK0_WRITE_EVENT0_BE_MASK               0x00000004
#define BANK0_WRITE_EVENT0_BE_GET(x)             (((x) & BANK0_WRITE_EVENT0_BE_MASK) >> BANK0_WRITE_EVENT0_BE_LSB)
#define BANK0_WRITE_EVENT0_BE_SET(x)             (((x) << BANK0_WRITE_EVENT0_BE_LSB) & BANK0_WRITE_EVENT0_BE_MASK)
#define BANK0_WRITE_EVENT0_WE_MSB                1
#define BANK0_WRITE_EVENT0_WE_LSB                1
#define BANK0_WRITE_EVENT0_WE_MASK               0x00000002
#define BANK0_WRITE_EVENT0_WE_GET(x)             (((x) & BANK0_WRITE_EVENT0_WE_MASK) >> BANK0_WRITE_EVENT0_WE_LSB)
#define BANK0_WRITE_EVENT0_WE_SET(x)             (((x) << BANK0_WRITE_EVENT0_WE_LSB) & BANK0_WRITE_EVENT0_WE_MASK)
#define BANK0_WRITE_EVENT0_CS_MSB                0
#define BANK0_WRITE_EVENT0_CS_LSB                0
#define BANK0_WRITE_EVENT0_CS_MASK               0x00000001
#define BANK0_WRITE_EVENT0_CS_GET(x)             (((x) & BANK0_WRITE_EVENT0_CS_MASK) >> BANK0_WRITE_EVENT0_CS_LSB)
#define BANK0_WRITE_EVENT0_CS_SET(x)             (((x) << BANK0_WRITE_EVENT0_CS_LSB) & BANK0_WRITE_EVENT0_CS_MASK)

#define BANK1_ADDR_ADDRESS                       0x0c004010
#define BANK1_ADDR_OFFSET                        0x00000010
#define BANK1_ADDR_SIZE_MSB                      31
#define BANK1_ADDR_SIZE_LSB                      28
#define BANK1_ADDR_SIZE_MASK                     0xf0000000
#define BANK1_ADDR_SIZE_GET(x)                   (((x) & BANK1_ADDR_SIZE_MASK) >> BANK1_ADDR_SIZE_LSB)
#define BANK1_ADDR_SIZE_SET(x)                   (((x) << BANK1_ADDR_SIZE_LSB) & BANK1_ADDR_SIZE_MASK)
#define BANK1_ADDR_BASE_MSB                      27
#define BANK1_ADDR_BASE_LSB                      10
#define BANK1_ADDR_BASE_MASK                     0x0ffffc00
#define BANK1_ADDR_BASE_GET(x)                   (((x) & BANK1_ADDR_BASE_MASK) >> BANK1_ADDR_BASE_LSB)
#define BANK1_ADDR_BASE_SET(x)                   (((x) << BANK1_ADDR_BASE_LSB) & BANK1_ADDR_BASE_MASK)

#define BANK1_CONFIG_ADDRESS                     0x0c004014
#define BANK1_CONFIG_OFFSET                      0x00000014
#define BANK1_CONFIG_ENABLE_MSB                  31
#define BANK1_CONFIG_ENABLE_LSB                  31
#define BANK1_CONFIG_ENABLE_MASK                 0x80000000
#define BANK1_CONFIG_ENABLE_GET(x)               (((x) & BANK1_CONFIG_ENABLE_MASK) >> BANK1_CONFIG_ENABLE_LSB)
#define BANK1_CONFIG_ENABLE_SET(x)               (((x) << BANK1_CONFIG_ENABLE_LSB) & BANK1_CONFIG_ENABLE_MASK)
#define BANK1_CONFIG_WIDTH_MSB                   28
#define BANK1_CONFIG_WIDTH_LSB                   28
#define BANK1_CONFIG_WIDTH_MASK                  0x10000000
#define BANK1_CONFIG_WIDTH_GET(x)                (((x) & BANK1_CONFIG_WIDTH_MASK) >> BANK1_CONFIG_WIDTH_LSB)
#define BANK1_CONFIG_WIDTH_SET(x)                (((x) << BANK1_CONFIG_WIDTH_LSB) & BANK1_CONFIG_WIDTH_MASK)
#define BANK1_CONFIG_PROTECT_MSB                 26
#define BANK1_CONFIG_PROTECT_LSB                 26
#define BANK1_CONFIG_PROTECT_MASK                0x04000000
#define BANK1_CONFIG_PROTECT_GET(x)              (((x) & BANK1_CONFIG_PROTECT_MASK) >> BANK1_CONFIG_PROTECT_LSB)
#define BANK1_CONFIG_PROTECT_SET(x)              (((x) << BANK1_CONFIG_PROTECT_LSB) & BANK1_CONFIG_PROTECT_MASK)
#define BANK1_CONFIG_WB_ENABLE_MSB               25
#define BANK1_CONFIG_WB_ENABLE_LSB               25
#define BANK1_CONFIG_WB_ENABLE_MASK              0x02000000
#define BANK1_CONFIG_WB_ENABLE_GET(x)            (((x) & BANK1_CONFIG_WB_ENABLE_MASK) >> BANK1_CONFIG_WB_ENABLE_LSB)
#define BANK1_CONFIG_WB_ENABLE_SET(x)            (((x) << BANK1_CONFIG_WB_ENABLE_LSB) & BANK1_CONFIG_WB_ENABLE_MASK)
#define BANK1_CONFIG_WB_FLUSH_MSB                24
#define BANK1_CONFIG_WB_FLUSH_LSB                24
#define BANK1_CONFIG_WB_FLUSH_MASK               0x01000000
#define BANK1_CONFIG_WB_FLUSH_GET(x)             (((x) & BANK1_CONFIG_WB_FLUSH_MASK) >> BANK1_CONFIG_WB_FLUSH_LSB)
#define BANK1_CONFIG_WB_FLUSH_SET(x)             (((x) << BANK1_CONFIG_WB_FLUSH_LSB) & BANK1_CONFIG_WB_FLUSH_MASK)
#define BANK1_CONFIG_SCALE_MSB                   21
#define BANK1_CONFIG_SCALE_LSB                   20
#define BANK1_CONFIG_SCALE_MASK                  0x00300000
#define BANK1_CONFIG_SCALE_GET(x)                (((x) & BANK1_CONFIG_SCALE_MASK) >> BANK1_CONFIG_SCALE_LSB)
#define BANK1_CONFIG_SCALE_SET(x)                (((x) << BANK1_CONFIG_SCALE_LSB) & BANK1_CONFIG_SCALE_MASK)
#define BANK1_CONFIG_HOLDOFF_MSB                 19
#define BANK1_CONFIG_HOLDOFF_LSB                 16
#define BANK1_CONFIG_HOLDOFF_MASK                0x000f0000
#define BANK1_CONFIG_HOLDOFF_GET(x)              (((x) & BANK1_CONFIG_HOLDOFF_MASK) >> BANK1_CONFIG_HOLDOFF_LSB)
#define BANK1_CONFIG_HOLDOFF_SET(x)              (((x) << BANK1_CONFIG_HOLDOFF_LSB) & BANK1_CONFIG_HOLDOFF_MASK)
#define BANK1_CONFIG_TIMER3_MSB                  15
#define BANK1_CONFIG_TIMER3_LSB                  12