//------------------------------------------------------------------------------
// <copyright file="rtc_reg.h" company="Atheros">
//    Copyright (c) 2006 Microsoft Corporation.  All rights reserved.
//    Copyright (c) 2006 Atheros Corporation.  All rights reserved.
//
//    The use and distribution terms for this software are covered by the
//    Microsoft Limited Permissive License (Ms-LPL) 
//    http://www.microsoft.com/resources/sharedsource/licensingbasics/limitedpermissivelicense.mspx 
//    which can be found in the file MS-LPL.txt at the root of this distribution.
//    By using this software in any fashion, you are agreeing to be bound by
//    the terms of this license.
//
//    You must not remove this notice, or any other, from this software.
// </copyright>
// 
// <summary>
//    Windows CE Wifi Driver for AR-6000
// </summary>
//------------------------------------------------------------------------------
//==============================================================================
// RTC registers definition
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _RTC_REG_H_
#define _RTC_REG_H_

#define RESET_CONTROL_ADDRESS                    0x0c000000
#define RESET_CONTROL_OFFSET                     0x00000000
#define RESET_CONTROL_RST_OUT_MSB                9
#define RESET_CONTROL_RST_OUT_LSB                9
#define RESET_CONTROL_RST_OUT_MASK               0x00000200
#define RESET_CONTROL_RST_OUT_GET(x)             (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
#define RESET_CONTROL_RST_OUT_SET(x)             (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
#define RESET_CONTROL_COLD_RST_MSB               8
#define RESET_CONTROL_COLD_RST_LSB               8
#define RESET_CONTROL_COLD_RST_MASK              0x00000100
#define RESET_CONTROL_COLD_RST_GET(x)            (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
#define RESET_CONTROL_COLD_RST_SET(x)            (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
#define RESET_CONTROL_WARM_RST_MSB               7
#define RESET_CONTROL_WARM_RST_LSB               7
#define RESET_CONTROL_WARM_RST_MASK              0x00000080
#define RESET_CONTROL_WARM_RST_GET(x)            (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
#define RESET_CONTROL_WARM_RST_SET(x)            (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
#define RESET_CONTROL_CPU_WARM_RST_MSB           6
#define RESET_CONTROL_CPU_WARM_RST_LSB           6
#define RESET_CONTROL_CPU_WARM_RST_MASK          0x00000040
#define RESET_CONTROL_CPU_WARM_RST_GET(x)        (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
#define RESET_CONTROL_CPU_WARM_RST_SET(x)        (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
#define RESET_CONTROL_MAC_COLD_RST_MSB           5
#define RESET_CONTROL_MAC_COLD_RST_LSB           5
#define RESET_CONTROL_MAC_COLD_RST_MASK          0x00000020
#define RESET_CONTROL_MAC_COLD_RST_GET(x)        (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
#define RESET_CONTROL_MAC_COLD_RST_SET(x)        (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
#define RESET_CONTROL_MAC_WARM_RST_MSB           4
#define RESET_CONTROL_MAC_WARM_RST_LSB           4
#define RESET_CONTROL_MAC_WARM_RST_MASK          0x00000010
#define RESET_CONTROL_MAC_WARM_RST_GET(x)        (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
#define RESET_CONTROL_MAC_WARM_RST_SET(x)        (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
#define RESET_CONTROL_MBOX_RST_MSB               2
#define RESET_CONTROL_MBOX_RST_LSB               2
#define RESET_CONTROL_MBOX_RST_MASK              0x00000004
#define RESET_CONTROL_MBOX_RST_GET(x)            (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
#define RESET_CONTROL_MBOX_RST_SET(x)            (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
#define RESET_CONTROL_UART_RST_MSB               1
#define RESET_CONTROL_UART_RST_LSB               1
#define RESET_CONTROL_UART_RST_MASK              0x00000002
#define RESET_CONTROL_UART_RST_GET(x)            (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
#define RESET_CONTROL_UART_RST_SET(x)            (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
#define RESET_CONTROL_SI0_RST_MSB                0
#define RESET_CONTROL_SI0_RST_LSB                0
#define RESET_CONTROL_SI0_RST_MASK               0x00000001
#define RESET_CONTROL_SI0_RST_GET(x)             (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
#define RESET_CONTROL_SI0_RST_SET(x)             (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)

#define XTAL_CONTROL_ADDRESS                     0x0c000004
#define XTAL_CONTROL_OFFSET                      0x00000004
#define XTAL_CONTROL_TCXO_MSB                    0
#define XTAL_CONTROL_TCXO_LSB                    0
#define XTAL_CONTROL_TCXO_MASK                   0x00000001
#define XTAL_CONTROL_TCXO_GET(x)                 (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
#define XTAL_CONTROL_TCXO_SET(x)                 (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)

#define TCXO_DETECT_ADDRESS                      0x0c000008
#define TCXO_DETECT_OFFSET                       0x00000008
#define TCXO_DETECT_PRESENT_MSB                  0
#define TCXO_DETECT_PRESENT_LSB                  0
#define TCXO_DETECT_PRESENT_MASK                 0x00000001
#define TCXO_DETECT_PRESENT_GET(x)               (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
#define TCXO_DETECT_PRESENT_SET(x)               (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)

#define XTAL_TEST_ADDRESS                        0x0c00000c
#define XTAL_TEST_OFFSET                         0x0000000c
#define XTAL_TEST_NOTCXODET_MSB                  0
#define XTAL_TEST_NOTCXODET_LSB                  0
#define XTAL_TEST_NOTCXODET_MASK                 0x00000001
#define XTAL_TEST_NOTCXODET_GET(x)               (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
#define XTAL_TEST_NOTCXODET_SET(x)               (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)

#define QUADRATURE_ADDRESS                       0x0c000010
#define QUADRATURE_OFFSET                        0x00000010
#define QUADRATURE_ADC_MSB                       5
#define QUADRATURE_ADC_LSB                       4
#define QUADRATURE_ADC_MASK                      0x00000030
#define QUADRATURE_ADC_GET(x)                    (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
#define QUADRATURE_ADC_SET(x)                    (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
#define QUADRATURE_SEL_MSB                       2
#define QUADRATURE_SEL_LSB                       2
#define QUADRATURE_SEL_MASK                      0x00000004
#define QUADRATURE_SEL_GET(x)                    (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
#define QUADRATURE_SEL_SET(x)                    (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
#define QUADRATURE_DAC_MSB                       1
#define QUADRATURE_DAC_LSB                       0
#define QUADRATURE_DAC_MASK                      0x00000003
#define QUADRATURE_DAC_GET(x)                    (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
#define QUADRATURE_DAC_SET(x)                    (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)

#define PLL_CONTROL_ADDRESS                      0x0c000014
#define PLL_CONTROL_OFFSET                       0x00000014
#define PLL_CONTROL_DIG_TEST_CLK_MSB             20
#define PLL_CONTROL_DIG_TEST_CLK_LSB             20
#define PLL_CONTROL_DIG_TEST_CLK_MASK            0x00100000
#define PLL_CONTROL_DIG_TEST_CLK_GET(x)          (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
#define PLL_CONTROL_DIG_TEST_CLK_SET(x)          (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
#define PLL_CONTROL_MAC_OVERRIDE_MSB             19
#define PLL_CONTROL_MAC_OVERRIDE_LSB             19
#define PLL_CONTROL_MAC_OVERRIDE_MASK            0x00080000
#define PLL_CONTROL_MAC_OVERRIDE_GET(x)          (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
#define PLL_CONTROL_MAC_OVERRIDE_SET(x)          (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
#define PLL_CONTROL_NOPWD_MSB                    18
#define PLL_CONTROL_NOPWD_LSB                    18
#define PLL_CONTROL_NOPWD_MASK                   0x00040000
#define PLL_CONTROL_NOPWD_GET(x)                 (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
#define PLL_CONTROL_NOPWD_SET(x)                 (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
#define PLL_CONTROL_UPDATING_MSB                 17
#define PLL_CONTROL_UPDATING_LSB                 17
#define PLL_CONTROL_UPDATING_MASK                0x00020000
#define PLL_CONTROL_UPDATING_GET(x)              (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
#define PLL_CONTROL_UPDATING_SET(x)              (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
#define PLL_CONTROL_BYPASS_MSB                   16
#define PLL_CONTROL_BYPASS_LSB                   16
#define PLL_CONTROL_BYPASS_MASK                  0x00010000
#define PLL_CONTROL_BYPASS_GET(x)                (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
#define PLL_CONTROL_BYPASS_SET(x)                (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
#define PLL_CONTROL_REFDIV_MSB                   15
#define PLL_CONTROL_REFDIV_LSB                   12
#define PLL_CONTROL_REFDIV_MASK                  0x0000f000
#define PLL_CONTROL_REFDIV_GET(x)                (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
#define PLL_CONTROL_REFDIV_SET(x)                (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
#define PLL_CONTROL_DIV_MSB                      9
#define PLL_CONTROL_DIV_LSB                      0
#define PLL_CONTROL_DIV_MASK                     0x000003ff
#define PLL_CONTROL_DIV_GET(x)                   (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
#define PLL_CONTROL_DIV_SET(x)                   (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)

#define PLL_SETTLE_ADDRESS                       0x0c000018
#define PLL_SETTLE_OFFSET                        0x00000018
#define PLL_SETTLE_TIME_MSB                      10
#define PLL_SETTLE_TIME_LSB                      0
#define PLL_SETTLE_TIME_MASK                     0x000007ff
#define PLL_SETTLE_TIME_GET(x)                   (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
#define PLL_SETTLE_TIME_SET(x)                   (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)

#define XTAL_SETTLE_ADDRESS                      0x0c00001c
#define XTAL_SETTLE_OFFSET                       0x0000001c
#define XTAL_SETTLE_TIME_MSB                     6
#define XTAL_SETTLE_TIME_LSB                     0
#define XTAL_SETTLE_TIME_MASK                    0x0000007f
#define XTAL_SETTLE_TIME_GET(x)                  (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
#define XTAL_SETTLE_TIME_SET(x)                  (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)

#define CORE_CLOCK_ADDRESS                       0x0c000020
#define CORE_CLOCK_OFFSET                        0x00000020
#define CORE_CLOCK_DIG_TEST_MSB                  12
#define CORE_CLOCK_DIG_TEST_LSB                  12
#define CORE_CLOCK_DIG_TEST_MASK                 0x00001000
#define CORE_CLOCK_DIG_TEST_GET(x)               (((x) & CORE_CLOCK_DIG_TEST_MASK) >> CORE_CLOCK_DIG_TEST_LSB)
#define CORE_CLOCK_DIG_TEST_SET(x)               (((x) << CORE_CLOCK_DIG_TEST_LSB) & CORE_CLOCK_DIG_TEST_MASK)
#define CORE_CLOCK_STANDARD_MSB                  9
#define CORE_CLOCK_STANDARD_LSB                  8
#define CORE_CLOCK_STANDARD_MASK                 0x00000300
#define CORE_CLOCK_STANDARD_GET(x)               (((x) & CORE_CLOCK_STANDARD_MASK) >> CORE_CLOCK_STANDARD_LSB)
#define CORE_CLOCK_STANDARD_SET(x)               (((x) << CORE_CLOCK_STANDARD_LSB) & CORE_CLOCK_STANDARD_MASK)
#define CORE_CLOCK_REDUCED_MSB                   1
#define CORE_CLOCK_REDUCED_LSB                   0
#define CORE_CLOCK_REDUCED_MASK                  0x00000003