/////////////////////////////////////////////////////////////////////////                                                             ////////  Protocol Engine                                            ////////  Performs automatic protocol functions                      ////////                                                             ////////  Author: Rudolf Usselmann                                   ////////          rudi@asics.ws                                      ////////                                                             ////////                                                             ////////  Downloaded from: http://www.opencores.org/cores/usb/       ////////                                                             /////////////////////////////////////////////////////////////////////////////                                                             //////// Copyright (C) 2000-2003 Rudolf Usselmann                    ////////                         www.asics.ws                        ////////                         rudi@asics.ws                       ////////                                                             //////// This source file may be used and distributed without        //////// restriction provided that this copyright statement is not   //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer.////////                                                             ////////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     //////// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   //////// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   //////// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      //////// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         //////// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    //////// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   //////// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        //////// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  //////// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  //////// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  //////// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         //////// POSSIBILITY OF SUCH DAMAGE.                                 ////////                                                             ///////////////////////////////////////////////////////////////////////////  CVS Log////  $Id: usbf_pe.v,v 1.8 2003/10/17 02:36:57 rudi Exp $////  $Date: 2003/10/17 02:36:57 $//  $Revision: 1.8 $//  $Author: rudi $//  $Locker:  $//  $State: Exp $//// Change History://               $Log: usbf_pe.v,v $//               Revision 1.8  2003/10/17 02:36:57  rudi//               - Disabling bit stuffing and NRZI encoding during speed negotiation//               - Now the core can send zero size packets//               - Fixed register addresses for some of the higher endpoints//                 (conversion between decimal/hex was wrong)//               - The core now does properly evaluate the function address to//                 determine if the packet was intended for it.//               - Various other minor bugs and typos////               Revision 1.7  2001/11/04 12:22:45  rudi////               - Fixed previous fix (brocke something else ...)//               - Majore Synthesis cleanup////               Revision 1.6  2001/11/03 03:26:22  rudi////               - Fixed several interrupt and error condition reporting bugs////               Revision 1.5  2001/09/24 01:15:28  rudi////               Changed reset to be active high async.////               Revision 1.4  2001/09/23 08:39:33  rudi////               Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ...////               Revision 1.3  2001/09/13 13:14:02  rudi////               Fixed a problem that would sometimes prevent the core to come out of//               reset and immediately be operational ...////               Revision 1.2  2001/08/10 08:48:33  rudi////               - Changed IO names to be more clear.//               - Uniquifyed define names to be core specific.////               Revision 1.1  2001/08/03 05:30:09  rudi//////               1) Reorganized directory structure////               Revision 1.2  2001/03/31 13:00:51  rudi////               - Added Core configuration//               - Added handling of OUT packets less than MAX_PL_SZ in DMA mode//               - Modified WISHBONE interface and sync logic//               - Moved SSRAM outside the core (added interface)//               - Many small bug fixes ...////               Revision 1.0  2001/03/07 09:17:12  rudi//////               Changed all revisions to revision 1.0. This is because OpenCores CVS//               interface could not handle the original '0.1' revision ....////               Revision 0.2  2001/03/07 09:08:13  rudi////               Added USB control signaling (Line Status) block. Fixed some minor//               typos, added resume bit and signal.////               Revision 0.1.0.1  2001/02/28 08:11:07  rudi//               Initial Release////`include "usbf_defines.v"module usbf_pe(	clk, rst,		// UTMI Interfaces		tx_valid, rx_active,		// PID Information		pid_OUT, pid_IN, pid_SOF, pid_SETUP,		pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA,		pid_ACK, pid_NACK, pid_STALL, pid_NYET,		pid_PRE, pid_ERR, pid_SPLIT, pid_PING,		// Speed Mode		mode_hs,		// Token Information		token_valid, crc5_err,		// Receive Data Output		rx_data_valid, rx_data_done, crc16_err,		// Packet Assembler Interface		send_token, token_pid_sel,		data_pid_sel, send_zero_length,		// IDMA Interface		rx_dma_en, tx_dma_en,		abort, idma_done,		adr, size, buf_size,		sizu_c, dma_en,		// Register File Interface		fsel, idin,		dma_in_buf_sz1, dma_out_buf_avail,		ep_sel, match, nse_err,		buf0_rl, buf0_set, buf1_set,		uc_bsel_set, uc_dpd_set,		int_buf1_set, int_buf0_set, int_upid_set,		int_crc16_set, int_to_set, int_seqerr_set,		out_to_small,		csr, buf0, buf1		);parameter	SSRAM_HADR = 14;input		clk, rst;input		tx_valid, rx_active;// Packet Disassembler Interface		// Decoded PIDs (used when token_valid is asserted)input		pid_OUT, pid_IN, pid_SOF, pid_SETUP;input		pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA;input		pid_ACK, pid_NACK, pid_STALL, pid_NYET;input		pid_PRE, pid_ERR, pid_SPLIT, pid_PING;input		mode_hs;input		token_valid;		// Token is validinput		crc5_err;		// Token crc5 errorinput		rx_data_valid;		// Data on rx_data_st is validinput		rx_data_done;		// Indicates end of a transferinput		crc16_err;		// Data packet CRC 16 error// Packet Assembler Interfaceoutput		send_token;output	[1:0]	token_pid_sel;output	[1:0]	data_pid_sel;output		send_zero_length;// IDMA Interfaceoutput		rx_dma_en;	// Allows the data to be storedoutput		tx_dma_en;	// Allows for data to be retrievedoutput		abort;		// Abort Transfer (time_out, crc_err or rx_error)input		idma_done;	// DMA is done indicatoroutput	[SSRAM_HADR + 2:0]	adr;		// Byte Addressoutput	[13:0]	size;		// Size in bytesoutput	[13:0]	buf_size;	// Actual buffer sizeinput	[10:0]	sizu_c;		// Up and Down counting size registers, used to updateoutput		dma_en;		// USB external DMA mode enabled// Register File interfaceinput		fsel;		// This function is selectedoutput	[31:0]	idin;		// Data Outputinput	[3:0]	ep_sel;		// Endpoint Number Inputinput		match;		// Endpoint Matchedoutput		nse_err;	// no such endpoint errorinput		dma_in_buf_sz1, dma_out_buf_avail;output		buf0_rl;	// Reload Buf 0 with original valuesoutput		buf0_set;	// Write to buf 0output		buf1_set;	// Write to buf 1output		uc_bsel_set;	// Write to the uc_bsel fieldoutput		uc_dpd_set;	// Write to the uc_dpd fieldoutput		int_buf1_set;	// Set buf1 full/empty interruptoutput		int_buf0_set;	// Set buf0 full/empty interruptoutput		int_upid_set;	// Set unsupported PID interruptoutput		int_crc16_set;	// Set CRC16 error interruptoutput		int_to_set;	// Set time out interruptoutput		int_seqerr_set;	// Set PID sequence error interruptoutput		out_to_small;	// OUT packet was to small for DMA operationinput	[31:0]	csr;		// Internal CSR Outputinput	[31:0]	buf0;		// Internal Buf 0 Outputinput	[31:0]	buf1;		// Internal Buf 1 Output/////////////////////////////////////////////////////////////////////// Local Wires and Registers//// tx token decodingparameter	ACK   = 0,		NACK  = 1,		STALL = 2,		NYET  = 3;// State decodingparameter	[9:0]	// synopsys enum state		IDLE	= 10'b000000_0001,		TOKEN	= 10'b000000_0010,		IN	= 10'b000000_0100,		IN2	= 10'b000000_1000,		OUT	= 10'b000001_0000,		OUT2A	= 10'b000010_0000,		OUT2B	= 10'b000100_0000,		UPDATEW	= 10'b001000_0000,		UPDATE	= 10'b010000_0000,		UPDATE2	= 10'b100000_0000;reg	[1:0]	token_pid_sel;reg	[1:0]	token_pid_sel_d;reg		send_token;reg		send_token_d;reg		rx_dma_en, tx_dma_en;reg		int_seqerr_set_d;reg		int_seqerr_set;reg		int_upid_set;reg		match_r;// Endpoint Decodingwire		IN_ep, OUT_ep, CTRL_ep;		// Endpoint Typeswire		txfr_iso, txfr_bulk;		// Transfer Typeswire		ep_disabled, ep_stall;		// Endpoint forced conditionswire		lrg_ok, sml_ok;		// Packet size acceptancewire	[1:0]	tr_fr;			// Number of transfers per micro-framewire	[10:0]	max_pl_sz;		// Max payload sizewire	[1:0]	uc_dpd, uc_bsel;// Buffer checkswire		buf_sel;reg		buf0_na, buf1_na;wire	[SSRAM_HADR + 2:0]	buf0_adr, buf1_adr;wire	[13:0]	buf0_sz, buf1_sz;reg	[9:0]	/* synopsys enum state */ state, next_state;// synopsys state_vector state// PID next and current decodersreg	[1:0]	next_dpid;reg	[1:0]	this_dpid;reg		pid_seq_err;wire	[1:0]	tr_fr_d;wire	[13:0]	size_next;wire		buf_smaller;reg	[SSRAM_HADR + 2:0]	adr;reg	[13:0]	new_size;reg	[13:0]	new_sizeb;reg		buffer_full;reg		buffer_empty;wire	[SSRAM_HADR + 2:0]	new_adr;reg		buffer_done;reg		no_bufs0, no_bufs1;wire		no_bufs;// After sending Data in response to an IN token from host, the// host must reply with an ack. The host has XXXnS to reply.// "rx_ack_to" indicates when this time has expired.// rx_ack_to_clr, clears the timerreg		rx_ack_to_clr;reg		rx_ack_to_clr_d;reg		rx_ack_to;reg	[7:0]	rx_ack_to_cnt;// After sending a OUT token the host must send a data packet.// The host has XX nS to send the packet. "tx_data_to" indicates// when this time has expired.// tx_data_to_clr, clears the timerwire		tx_data_to_clr;reg		tx_data_to;reg	[7:0]	tx_data_to_cnt;wire	[7:0]	rx_ack_to_val, tx_data_to_val;reg		int_set_en;wire	[1:0]	next_bsel;reg		buf_set_d;reg		uc_stat_set_d;reg	[31:0]	idin;reg		buf0_set, buf1_set;reg		uc_bsel_set;reg		uc_dpd_set;reg		buf0_rl_d;reg		buf0_rl;wire		no_buf0_dma;reg		buf0_st_max;reg		buf1_st_max;reg	[SSRAM_HADR + 2:0]	adr_r;reg	[13:0]	size_next_r;reg		in_token;reg		out_token;reg		setup_token;wire		in_op, out_op;	// Indicate a IN or OUT operationreg		to_small;	// Indicates a "to small packer" errorreg		to_large;	// Indicates a "to large packer" errorreg		buffer_overflow;reg	[1:0]	allow_pid;reg		nse_err;reg		out_to_small, out_to_small_r;reg		abort;reg		buf0_not_aloc, buf1_not_aloc;reg		send_zero_length;/////////////////////////////////////////////////////////////////////// Misc Logic//// Endpoint/CSR Decodingassign IN_ep   = csr[27:26]==2'b01;assign OUT_ep  = csr[27:26]==2'b10;assign CTRL_ep = csr[27:26]==2'b00;