--1.控制模塊
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY control IS
       PORT (clk0,reset0,s0,s1,c0 :IN STD_LOGIC;
             ld0 :out std_logic; 
             dinl0,dinh0 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
             state0 :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END control;
ARCHITECTURE behav1 OF control IS
 signal statenum:std_logic_vector(2 downto 0);
 signal ldt:std_logic;
 signal reg:std_logic_vector(5 downto 0);
 BEGIN
  state0<=statenum;
  ld0<=ldt;
  reg<=statenum&s0&s1&c0;
  process(reg,clk0)
  begin
   if reset0='0' then
      statenum<="000";dinh0<="0010";dinl0<="1001";ldt<='0';
   elsif clk0'event and clk0='0' then 
         case reg is when "000001"|"000011"|"000101"|"000111" =>
                          statenum<="001";dinh0<="0000";dinl0<="0100";ldt<='0';
                     when "001001" |"001011"|"001101" |"001111"=>
                          statenum<="010";dinh0<="0001";dinl0<="1001";ldt<='0';
                     when "010001"|"010011"|"010101"|"010111" =>
                          statenum<="011";dinh0<="0000";dinl0<="0100";ldt<='0';
                     when "011001" =>
                          statenum<="000";dinh0<="0010";dinl0<="1001";ldt<='0';
                     when "011011"|"011111" =>
                          statenum<="100";dinh0<="0000";dinl0<="1001";ldt<='0';
                     when "011101" =>
                          statenum<="110";dinh0<="0000";dinl0<="1001";ldt<='0';
                     when "100000"|"100100"|"100001"|"100101"|"100011"|"100111"=>
                          statenum<="101";dinh0<="0000";dinl0<="0100";ldt<='0';
                     when "101101"|"101111" =>
                          statenum<="110";dinh0<="0000";dinl0<="1001";ldt<='0';
                     when "101011"|"101001" =>
                          statenum<="000";dinh0<="0010";dinl0<="1001";ldt<='0';
                     when "110000"|"110010"|"110001"|"110011"|"110101"|"110111"=>
                          statenum<="111";dinh0<="0000";dinl0<="0100";ldt<='0';
                     when "111001"|"111011"|"111101"|"111111" =>
                          statenum<="000";dinh0<="0010";dinl0<="1001";ldt<='0';
                     when others =>
                          ldt<='1';
          end case;
   end if;
  end process;
end behav1;
--2.計數模塊
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mvc is
 port( cp1:in std_logic;
       ld1:in std_logic;
       dinl1:in std_logic_vector(3 downto 0);
       dinh1:in std_logic_vector(3 downto 0);
       ql1:out std_logic_vector(3 downto 0);
       qh1:out std_logic_vector(3 downto 0);
       c1:out std_logic);
end mvc;
architecture behav2 of mvc is
 signal qa,qat:std_logic_vector(3 downto 0);
 signal qb,qbt:std_logic_vector(3 downto 0);
 signal ca:std_logic;
 begin
  qh1<=qb;
  ql1<=qa;
  process(cp1)
  begin
   qat<=dinl1; 
   if cp1'event and cp1='1' then
      if ld1='0' then qa<=qat;ca<='0';
      elsif(qa="0000" and qb="0000") then qa<="0000";
      elsif(qa="0000") then qa<="1001";ca<='0';
      elsif(qa="0001") then ca<='1';qa<="0000";
      else qa<=qa-1;ca<='0';
      end if;
      
   end if;
  end process;
  process(ca,cp1)
  begin
   qbt<=dinh1;
   if cp1'event and cp1='1' then
     if ld1='0' then qb<=qbt;c1<='0';
     elsif(qb="0000" and qa="0000") then qb<="0000";
     elsif(qb="0000" and qa="0001") then c1<='1';
     elsif(ca='1') then qb<=qb-1;
     end if;
   end if;
  end process;
end behav2;
--3.信號燈模塊
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY tolight IS
   PORT (clk2:IN STD_LOGIC;
         statenum2:in STD_LOGIC_VECTOR(2 DOWNTO 0);
         n,s,e,w:out STD_LOGIC_VECTOR(3 DOWNTO 0));
END tolight;
ARCHITECTURE behav3 OF tolight IS
begin
process(clk2)
 begin
  if clk2'event and clk2='1' then
     case statenum2(2 downto 0) is
          when "000"=>s<="0100";n<="0100";e<="0001";w<="0001";
          when "001"=>s<="0010";n<="0010";e<="0001";w<="0001";
          when "010"=>s<="1000";n<="1000";e<="0001";w<="0001";
          when "011"=>s<="0010";n<="0010";e<="0001";w<="0001";
          when "100"=>s<="0001";n<="0001";e<="1100";w<="0001";
          when "101"=>s<="0001";n<="0001";e<="0010";w<="0001";
          when "110"=>s<="0001";n<="0001";e<="0001";w<="1100";
          when "111"=>s<="0001";n<="0001";e<="0001";w<="0010";
          when others=>s<="0100";n<="0100";e<="0001";w<="0001";
     end case;
   end if;
end process;
end behav3;
--4.頂層文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port(clk:in std_logic;
     se,sw :in std_logic;
     reset:in std_logic;
     sd,nd,ed,wd:OUT STD_LOGIC_vector(3 downto 0);
     time:out std_logic_vector(7 downto 0));
end traffic;
ARCHITECTURE behav OF traffic IS
 component control IS
  PORT (clk0,reset0,s0,s1,c0 :IN STD_LOGIC;
        ld0 :out std_logic;
        dinl0,dinh0 :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        state0 :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
 END component control;
 component mvc is
  port(cp1:in std_logic;
       ld1:in std_logic;
       dinl1:in std_logic_vector(3 downto 0);
       dinh1:in std_logic_vector(3 downto 0);
       ql1:out std_logic_vector(3 downto 0);
       qh1:out std_logic_vector(3 downto 0);
       c1:out std_logic);
 end component mvc;
 component tolight IS
  PORT (clk2:IN STD_LOGIC;
        statenum2:in STD_LOGIC_VECTOR(2 DOWNTO 0);
        s,n,e,w:OUT STD_LOGIC_vector(3 downto 0));
 END component tolight;
signal c,ld :std_logic;
signal dinl,dinh:std_logic_vector(3 downto 0);
signal statenum :std_logic_vector(2 downto 0);
begin
u1: control port map
(clk0=>clk,reset0=>reset,s0=>sw,s1=>se,c0=>c,ld0=>ld,dinl0=>dinl,dinh0=>dinh,state0=>statenum);
u2: mvc port map(cp1=>clk,ld1=>ld,dinl1=>dinl,dinh1=>dinh,ql1=>time(3 downto 0),qh1=>time(7 downto 4),c1=>c);
u3: tolight port map(clk2=>clk,statenum2=>statenum,s=>sd,n=>nd,e=>ed,w=>wd);
end behav;