neg
				sacl		i1
				spm			0
*****************end current sampling---AD conversions
************************************************************
***sampled current scaling and
***(a,b,c)->(alfa,beta)axis transformation
***ialfa=i1
***ibeta=(i*i2+i1)/sqrt(3)
************************************************************
				lacc		i1
				sacl		ialfa
				
				lacc		i2,1
				add			i1
				sacl		tmp
				lt			tmp
				mpy			sqrt3inv
				pac
				sach		ibeta,4
*******end sampled current scaling and (a,b,c)->(alfa,beta) axis transformation

*****************************************************
**sin and cosine wave calculation from theta values using sine look-up table
*****************************************************
				lacc		theta
				
				rpt			#3
				sfr
				and			#0ffh
				sacl		indice1
				add			#sintab
				sacl		tmp
				nop
				nop
				mar			*,ar5
				lacl		*
				nop
				sacl		seno1
				
				lacl		indice1
				add			#040h
				and			#0ffh
				sacl		indice1
				add			#sintab
				sacl		tmp
				lar			ar5,tmp
				lacc		*
				sacl		coseno
******end sine and cosine wave calculation
***************************************************
***d-axis and q-axis current calculation
***(alfa,beta)->(d,q)axis transformation
***id=ialfa*cos(theta)+ibeta*sin(theta)
***iq=-ialfa*sin(theta)+ibeta*cos(theta)
*****************************************************
				lacc		#0
				lt			ibeta
				mpy			seno1
				lta			ialfa
				mpy			coseno
				mpya		seno1
				sach		id,4
				lacc		#0
				lt			ibeta
				mpys		coseno
				apac
				sach		iq,4
***********end d-axis and q-axis current calculation
*******************************************************
***q-axis current regulator with integral component
***(iq,iqr)->(vqr)
******************************************************
				lacc		iqr
				sub			iq
				sacl		epiq
				lacc		xiq,12
				lt			epiq
				mpy			kpi
				apac
				sach		upi,4
				
				bit			upi,0
				bcnd		upimagzeroq,ntc
				lacc		#vmin
				sub			upi
				bcnd		neg_satq,gt
				
				lacc		upi
				b			limiterq
neg_satq:
				lacc		#vmin
				b			limiterq
upimagzeroq:
				lacc		#vmax
				sub			upi
				bcnd		pos_satq,lt
				lacc		upi
				b			limiterq
pos_satq:
				lacc		#vmax
limiterq:
				sacl		vqr
				sub			upi
				sacl		elpi
				lt			elpi
				mpy			kcor
				pac
				lt			epiq
				mpy			ki
				apac
				add			xiq,12
				sach		xiq,4
*********end q-axis current regulator with integral component corrention
*******************************************************
***d-axis current regulator with integral component
***(id,idr)->(vdr)
******************************************************
				lacc		idr
				sub			id
				sacl		epid
				lacc		xid,12
				lt			epid
				mpy			kpi
				apac
				sach		upi,4
				
				bit			upi,0
				bcnd		upimagzerod,ntc
				lacc		#vmin
				sub			upi
				bcnd		neg_satd,gt
				
				lacc		upi
				b			limiterd
neg_satd:
				lacc		#vmin
				b			limiterd
upimagzerod:
				lacc		#vmax
				sub			upi
				bcnd		pos_satd,lt
				lacc		upi
				b			limiterd
pos_satd:
				lacc		#vmax
limiterd:
				sacl		vdr
				sub			upi
				sacl		elpi
				lt			elpi
				mpy			kcor
				pac
				lt			epid
				mpy			ki
				apac
				add			xid,12
				sach		xid,4 
*******end d-axis current regulator with integral
****************************************************************
**alfa-axis and beta-axis voltage calculation
**(d,q)->(alfa,beta) axis transformation
**vbetar=vqr*cos(theta)+vdr*sin(theta)
**valfar=-vqr*sin(theta)+vdr*cos(theta)
*****************************************************************
				lacc		#0
				lt			vdr
				mpy			seno1
				lta			vqr
				mpy			coseno
				mpya		seno1
				sach		vbetar,4
				lacc		#0
				lt			vdr
				mpys		coseno
				apac
				sach		valfar,4
***end alfa-axis and beta-axis voltage calculation
***************************************************************
***phase 1(=a) 2(=b) 3(=c)voltage calculation
***(alfa,beta)->(a,b,c)axis transformation
***ua=valfar
***ub=(-valfar+sqrt(3)*vbetar)/2
***uc=(-valfar-sqrt(3)*vbetar)/2
****************************************************************
				lt			vbetar
				mpy			sqrt32
				pac
				sub			valfar,11
				sach		ub,4
				pac
				neg
				sub			valfar,11
				sach		uc,4
				lacl		valfar
				sacl		ua
*******end phase 1 2 3 voltage calculation
***************************************************************
***phase 1(=a) 2(=b) 3(=c)voltage calculation
***(alfa,beta)->(a,b,c)axis transformation
***modified exchanging alfa axis with beta axis
***va=vbetar
***vb=(-vbetar+sqrt(3)*valfar)/2
***vc=(-vbetar-sqrt(3)*valfar)/2
**************************************************************** 
				lt			valfar
				mpy			sqrt32
				pac
				sub			vbetar,11
				sach		vb,4
				pac
				neg
				sub			vbetar,11
				sach		vc,4
				lacl		vbetar
				sacl		va
**********end phase 1 2 3 voltage calculation
******************************************************
***space vector pulse width modulation
******************************************************
				lt			vdcinvtc
				mpy			sqrt32
				pac
				sach		tmp,4
				lt			tmp
				mpy			vbetar
				pac
				sach		x,4
				lacc		x          		;acc=vbetar*k1
				sach		accb            
				sacl		accb+1          ;accb=vbetar*k1
				sacl		x,1             ;x=2*vbetar*k1
				lt			vdcinvtc
				splk		#1800h,tmp
				mpy			tmp
				pac
				sach		tmp,4
				lt			tmp
				mpy			valfar
				pac
				sach		tmp,4
				lacc		tmp     		;reload acc with valfar*k2
				add			accb+1
				add			accb,16
				sacl		y               ;y=k1*vbetar+k2*valfar
				sub			tmp,1
				sacl		z               ;z=k1*vnetar-K2*valfar
*****************60 degree sector determination
				lacl		#0
				sacl		sector
				lacc		va
				bcnd		va_neg,leq
				lacc		sector
				or			#1
				sacl		sector           ;implement op1 #1,sector
va_neg:
				lacc		vb
				bcnd		vb_neg,leq
				lacc		sector
				or			#2
				sacl		sector				;implement op1,#2,sector
vb_neg:
				lacc		vc
				bcnd		vc_neg,leq
				lacc		sector
				or			#4
				salc		sector				;implement op1,#4,sector
vc_neg:
****************end 60 degree determination
********T1 AND T2 calculation depengding on the sector number
				lacl		sector
				sub			#1
				bcnd		no1,neq
				lacc		z
				sacl		t1
				lacc		y
				sacl		t2
				b			t1t2out
no1:
				lacl		sector
				sub			#2
				bcnd		no2,neq
				lacc		y
				sacl		t1
				lacc		x
				neg
				sacl		t2
				b			t1t2out
no2:
				lacl		sector
				sub			#3
				bcnd		no3,neq
				lacc		z
				neg
				sacl		t1
				lacc		x
				sacl		t2
				b			t1t2out
no3:
				lacl		sector
				sub			#4
				bcnd		no4,neq
				lacc		x
				neg
				sacl		t1
				lacc		z
				sacl		t2
				b			t1t2out
no4:
				lacl		sector
				sub			#5
				bcnd		no5,neq
				lacc		x
				sacl		t1
				lacc		y
				neg
				sacl		t2
				b			t1t2out
no5:
				lacc		y
				neg
				sacl		t1
				lacc		z
				neg
				sacl		t2
t1t2out:
				lacc		t1				;t1 and t2 minumum values must be tonmax
				sub			#tonmax	
				bcnd		t1_ok,geq
				lacl		#tonmax
				sacl		t1
t1_ok:
				lacc		t2
				sub			#tonmax
				bcnd		t2_ok,geq
				lacl		#tonmax
				sacl		t2
t2_ok:
****************end t1 and t2 calculation
				lacc		t1				;if t1+t2>2*tonmax we have to saturate t1 and t2
				add			t2
				sacl		tmp
				sub			#maxduty
				bcnd		nosaturation,lt,eq
*******t1 and t2 saturation
				lacc		#maxduty,15		;divide maxduty by (t1+t2)
				rpt			#15
				subc		tmp
				sacl		tmp
				lt			tmp				;calculate saturate values of t1 and t2
				mpy			t1				;t1(saturated)=t1*(maxduty/(t1+t2))
				pac
				sach		t1,1
				mpy			t2
				pac
				sach		t2,1
*******end t1 and t2 saturation
nosaturation:
*******taon,tbon,tcon calculation
				lacc		#pwmprd
				sub			t1
				sub			t2
				sfr           				;tacon=(pwmprd-t1-t2)/2
				sacl		taon
				add			t1
				sacl		tbon			;tbon=taon+t1
				add			t2
				sacl		tcon			;tcon=taon+t2
*******end taon tbon tcon calculation
*************************************
*******sector switching
				lacl		sector
				sub			#1
				bcnd		nosect1,neq
				bldd		tbon,#CMPR1
				bldd		taon,#CMPR2
				bldd		tcon,#CMPR3
				b			daout
nosect1:
				lacl		sector
				sub			#2
				bcnd		nosect2,neq
				bldd		taon,#CMPR1
				bldd		tcon,#CMPR2
				bldd		tbon,#CMPR3
				b			daout
nosect2:
				lacl		sector
				sub			#3
				bcnd		nosect3,neq
				bldd		taon,#CMPR1
				bldd		tbon,#CMPR2
				bldd		tcon,#CMPR3
				b			daout
nosect3:
				lacl		sector
				sub			#4
				bcnd		nosect4,neq
				bldd		tcon,#CMPR1
				bldd		tbon,#CMPR2
				bldd		taon,#CMPR3
				b			daout
nosect4:
				lacl		sector
				sub			#5
				bcnd		nosect5,neq
				bldd		tcon,#CMPR1
				bldd		baon,#CMPR2
				bldd		tbon,#CMPR3
				b			daout
nosect5:
				bldd		tbon,#CMPR1
				bldd		tcon,#CMPR2
				bldd		taon,#CMPR3
**********end sector switching
*******************************************
**DAC output of channels da1 da2 da3 da4
**output on 12 bit digital analog convert
**5v  equivalent to fffh
******************************************
daout:
				ldp			#sector
				lacc		sector,7			;scale sector by 2^7 to have good
				sacl		sectordisp	        ;displaying only for display purposes
*****DAC out channel da1
				lacc		#i1
				add			da1
				sacl		daout
				lar			ar5,daout
				lacc		*
				sfr
				sfr
				add			#800h
				sacl		daouttmp
				out			daouttmp,dac0_val
******end dac out channel da1
******dac out channel da2
				lacc		#i1
				add			da2
				sacl		daout
				lar			ar5,daout
				lacc		*
				sfr
				sfr
				add			#800h
				sacl		daouttmp
				out			daouttmp,dac1_val 
************************************************
				lacc		#i1
				add			da3
				sacl		daout
				lar			ar5,daout
				lacc		*
				sfr
				sfr
				add			#800h
				sacl		daouttmp
				out			daouttmp,dac2_val
******************************************************
				lacc		#i1
				add			da4
				sacl		daout
				lar			ar5,daout
				lacc		*
				sfr
				sfr
				add			#800h
				sacl		daouttmp
				out			daouttmp,dac3_val
*************end dac out channel da4
				out			tmp,dac_val			;start converrsion
				ldp			#ifra>>7
				splk		#0200h,ifra
				ldp			#DP_PF2
				splk		#0ff88h,PCDATDIR
				b			contextrestorereturn
*********end controlroutine
****************************************************
****************************************************
*******main program from here***********************
****************************************************
_c_int0:
				clrc		cnf
				clrc		xf
				
**********disable the watch dog timer****************
				ldp			#DP_PF1
				splk		#006fh,WDCNTR
				splk		#5555h,WDKEY
				splk		#0aaaah,WDKEY
				splk		#006fh,WDCNTR
*****************************************************
***function to initialize the event manager
*****************************************************
				ldp			#DP_PF1
				splk		#02h,ckcr0
				splk		#0b1h,ckcr1
				spk			#60h,ckcr1
				splk		#83h,ckcr0
				splk		#40c0h,syscr
				lacc		syssr
				and			#69ffh
				sacl		syssr