--聲明：
--本VHDL描述版權屬作者（Dick Hou）個人所以，任何人可以以此作學習之用，也可以散發(fā)傳播，但必須注明出處（可編程邏輯器件與單片機網站）。
--任何人可以將此作為以學習為目的的設計中，但不能用于商業(yè)產品中以謀取利益。


--	Spartan II FPGA Configuration use slave serial mode
--	FpgaConf.vhd
--	Dick Hou	2001/12/27
--	采用從串模式

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fpgaconf is
	port (	resetin	:in std_logic;		--接Spartan II 的/PROG腳，此腳通過上拉電阻接到VCC，并通過按鍵接GND，按下此鍵后開始配置
			init	:in std_logic;	--接Spartan II 的INIT腳
			done	:in std_logic;	--接Spartan II 的DONE腳
			clk	:in std_logic;	--系統(tǒng)時鐘輸入
			done_ok	:out std_logic;	--驅動LED指示燈，接LED陽極，指示配置成功與否
			din	:out std_logic;	--接Spartan II DIN腳
			cclk	:out std_logic;	--接Spartan II CCLK腳
			poe	:out std_logic;	--接配置ROM的/OE端，也可直接將/OE接地
			pce	:out std_logic;	--接配置ROM的/CE端，也可直接將/CE接地
			cdata	:in std_logic_vector(7 downto 0);	--接ROM的數(shù)據線
			caddr	:out std_logic_vector(18 downto 0)	--接ROM的地址線
		);
end fpgaconf;

architecture behav of fpgaconf is
signal	acnt	:std_logic_vector(21 downto 0);
signal	dreg	:std_logic_vector(8 downto 0);
signal	st0,st1,st2,st3,st4	:std_logic;
signal	en_cclk	:std_logic;
signal	clkdiv	:std_logic_vector(2 downto 0);
signal	clkin	:std_logic;

begin
	process(clk)
	begin
		if clk'event and clk='0' then
			clkdiv	<=clkdiv + 1;
		end if;
	end process;
	clkin	<=clkdiv(2);
	
	process(clkin,init,done,resetin)
	begin
		if clkin'event and clkin='0' then
			if resetin='0' then
				acnt<="0000000000000000000000";
				st0<='1';
				st1<='1';
				st2<='0';
				st3<='0';
				st4<='0';
				en_cclk<='1';
			elsif st1='1' then
				if init='0' then
					st0<='0';
					st1<='1';
					st2<='0';
					st3<='0';
					st4<='0';
					en_cclk<='1';
				else
					st0<='0';
					st1<='0';
					st2<='1';
					st3<='0';
					st4<='0';
					en_cclk<='0';
				end if;
			elsif st2='1' then
				if acnt(2 downto 0)<="000" then
					if done='1' then	--Configuration secucess;
						st0<='0';
						st1<='0';
						st2<='0';
						st3<='1';
						st4<='0';
						en_cclk<='0';
					elsif acnt(21 downto 3)="111111111111111111" then
						st0<='0';
						st1<='0';
						st2<='0';
						st3<='0';
						st4<='1';		--Configuration failure
						en_cclk<='1';
					else
						dreg(8 downto 1)<=cdata(7 downto 0);
						dreg(0)<=dreg(1);
						st0<='0';
						st1<='0';
						st2<='1';
						st3<='0';
						st4<='0';
						en_cclk<='0';
					end if;
				else
					dreg(8 downto 0)<='0'&dreg(8 downto 1);
					st0<='0';
					st1<='0';
					st2<='1';
					st3<='0';
					st4<='0';
					en_cclk<='0';
				end if;
				acnt<=acnt+1;
			elsif st3='1' then
				if acnt(2 downto 0)="111" then
					st0<='0';
					st1<='0';
					st2<='0';
					st3<='0';
					st4<='1';
					en_cclk<='1';	--End
				else
					st0<='0';
					st1<='0';
					st2<='0';
					st3<='1';
					st4<='0';
					en_cclk<='0';	--Continue
				end if;
				acnt<=acnt + 1;
			elsif st4='1' then
				st0<='0';
				st1<='0';
				st2<='0';
				st3<='0';
				st4<='1';
				en_cclk<='1';
			end if;
		end if;
	end process;
	done_ok<=not done;
	din<=dreg(0);
	cclk<=clkin or en_cclk;
	pce<=en_cclk;
	poe<=en_cclk;
	caddr<=acnt(21 downto 3);
end behav;