--*************************************************************************************--
--Colour Sort Machine dividing clock module V1.0/2003.12.20
--EIST Department,Nankai University
--Function f_clkout =(f_clkin/125)
--Src file:clock125.vhd
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock800 is
  port(clkin:in std_logic;     
       clkout5k:out std_logic; 
       clkout1:out std_logic 
       );
end entity;

architecture arc of clock800 is
begin
 process(clkin) 
  variable count1:integer range 0 to 800;
  variable count2:integer range 0 to 4000000;
  begin
    if (clkin'event and clkin='1') then
    	if count1>=799 then
    		count1:=0;
    	else
    		count1:=count1+1;	
    	end if;
    	case count1 is
    		when 0 to 399=>clkout5k<='0';
    		when others =>clkout5k<='1';
    	end case;
     if count2>=3999999 then
        count2:=0;
     else
        count2:=count2+1;
     end if;
     case count2 is
          when 0 to 1999999=>clkout1<='0';
    	  when others =>clkout1<='1'; 
     end case;     		
    end if;
  end process;
end arc;