?? block1.map.rpt
字號(hào):
Analysis & Synthesis report for Block1
Tue Aug 09 14:51:41 2005
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. Analysis & Synthesis Resource Utilization by Entity
6. Analysis & Synthesis Equations
7. Analysis & Synthesis Source Files Read
8. Analysis & Synthesis Resource Usage Summary
9. WYSIWYG Cells
10. General Register Statistics
11. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Aug 09 14:51:41 2005 ;
; Quartus II Version ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name ; Block1 ;
; Top-level Entity Name ; Block1 ;
; Family ; FLEX10K ;
; Total logic elements ; 255 ;
; Total pins ; 38 ;
; Total memory bits ; 0 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------+----------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+----------------+---------------+
; Device ; EPF10K10LC84-4 ; ;
; Family name ; FLEX10K ; Stratix ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; Block1 ; Block1 ;
; State Machine Processing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
+------------------------------------------------------+----------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
Block1
|-- AND1:inst
|-- ANDL:inst1
|-- lpm_counter:dou_rtl_0
|-- alt_counter_f10ke:wysi_counter
|-- ROM:inst2
|-- YIMAQI:inst3
|-- clock800:inst4
|-- lpm_add_sub:add_rtl_1
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- DELED:inst8
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
; |Block1 ; 255 (0) ; 18 ; 0 ; 38 ; 237 (0) ; 1 (0) ; 17 (0) ; 14 (0) ; |Block1 ;
; |AND1:inst| ; 3 (3) ; 3 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 2 (2) ; 0 (0) ; |Block1|AND1:inst ;
; |ANDL:inst1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |Block1|ANDL:inst1 ;
; |lpm_counter:dou_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |Block1|ANDL:inst1|lpm_counter:dou_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |Block1|ANDL:inst1|lpm_counter:dou_rtl_0|alt_counter_f10ke:wysi_counter ;
; |DELED:inst8| ; 6 (6) ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|DELED:inst8 ;
; |ROM:inst2| ; 209 (209) ; 0 ; 0 ; 0 ; 209 (209) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|ROM:inst2 ;
; |YIMAQI:inst3| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; |Block1|YIMAQI:inst3 ;
; |clock800:inst4| ; 26 (17) ; 11 ; 0 ; 0 ; 15 (6) ; 0 (0) ; 11 (11) ; 10 (1) ; |Block1|clock800:inst4 ;
; |lpm_add_sub:add_rtl_1| ; 9 (0) ; 0 ; 0 ; 0 ; 9 (0) ; 0 (0) ; 0 (0) ; 9 (0) ; |Block1|clock800:inst4|lpm_add_sub:add_rtl_1 ;
; |addcore:adder| ; 9 (1) ; 0 ; 0 ; 0 ; 9 (1) ; 0 (0) ; 0 (0) ; 9 (1) ; |Block1|clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder ;
; |a_csnbuffer:result_node| ; 8 (8) ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 0 (0) ; 8 (8) ; |Block1|clock800:inst4|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
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