?? andl.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ANDL is
port
(CKDSP,CR: in std_logic;
AD3,AD2,AD1,AD0: out std_logic);
end;
architecture ARC_ANDL of ANDL is
signal dou: std_logic_vector(3 downto 0);
begin
AD3<=dou(3);
AD2<=dou(2);
AD1<=dou(1);
AD0<=dou(0);
process(CKDSP,CR)
begin
if(CR='1')then
dou<="0000";
elsif(CKDSP'event and CKDSP='1')then
if(dou="1111")then
dou<="0000";
else
dou<=dou+1;
end if;
end if;
end process;
end ARC_ANDL;
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