?? clock2500.vhd
字號:
--*************************************************************************************--
--Colour Sort Machine dividing clock module V1.0/2003.12.20
--EIST Department,Nankai University
--Function f_clkout =(f_clkin/125)
--Src file:clock125.vhd
--*************************************************************************************--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock2500 is
port(clkin:in std_logic;
clkout:out std_logic
);
end entity;
architecture arc of clock2500 is
begin
process(clkin)
variable count:integer range 0 to 2500;
begin
if (clkin'event and clkin='1') then
if count>=2499 then
count:=0;
else
count:=count+1;
end if;
case count is
when 0 to 1249=>clkout<='0';
when others =>clkout<='1';
end case;
end if;
end process;
end arc;
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