//***************************************************************************
//                                                                           
// File:         MillerCode.v                                                      
//                                                                           
// Version:      1.0                                       	       		    
//                                                                           
// Created:      29.07.2006                                                  
// Last Change:                                                
//                                                                           
                         
//                                                                           
// Compiler:     NC-sim and MAXplus2                                             
//                                                                           
// Description:  The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero,
//               generates the flute when the posedge, MD_Counter8One,generates the flute when the negedge.The aim
//               of the module is to generate the mended miller code to be the source of the MillerDecode.     
//							 輸入的數據以下降沿采樣，有效輸入范圍為上升沿前一點，輸入數據包括1'b0+有效數據+1'b0
// Operating Rule: R_DATAUNCODE must be synchronous with R_ACTIVE             
//                                                              
//**************************************************************************
`timescale 1ns/1ns

module MillerCode(Test1, Test2, MC_DATACODE, R_DATAUNCODE, R_ACTIVE, CLK, FD_CLK128, RST_P);
output					Test1;
output					Test2;
output		  		MC_DATACODE;				// the data coded by mended miller code
input						R_DATAUNCODE;				// the data needs to be coded,the format is 0,1,1,...
input						R_ACTIVE;						// the valid range of the data to be coded,and it controls the start
                                    // and end of the MillerCode                               
input						CLK;								// the 13.56MHz clock source
input						FD_CLK128;          // the 1/128 13.56MHz clock     
input			    	RST_P;							// the global reset signal 

reg							CurrentData;				// sample the value of the R_DATAUNCODE,because flowing the ISO14443A,the
																		// last bit of the frame should be the high level,so the module use it.it
																		// would generate one clock delay	
reg							ZeroFlute;					// it means the zero bit should be generated a flute
reg							OneFlute;						// it means the one bit should be generated a flute

wire						ValidCLK;						// selcet the active range of the clock in order to low the power

reg							PreData;						// distinguish the flute between the current data and the previous data;

wire						reset_p;						// the reset signal
wire						reset_counter;
reg							reset_counterzero;
reg							reset_counterone;
reg							dff_q1;
reg							dff_q2;
reg							dff_q3;
reg							dff_q4;
reg							OutputValid;				//
reg							Pulse;						
reg							ValidCLK_N;					// 下降沿觸發采樣的時鐘信號
reg							NoneValidCLK_N;			// 下降沿觸發采樣的時鐘負邊沿
reg							active_flipflop;
reg							ZeroFlute_N;
reg							OneFlute_N;
reg							GatingValidCLK;
reg							GatingValidCLK_P;

// use the state machine to judge the operation that should generate the zero flute or one flute or not
parameter				P_StateLength = 2;				// the length of the state

parameter				[P_StateLength-1:0]
															P_ZeroVariable = 2'b00,
                							P_NoneVariable = 2'b01,  // the flute should be generated in the zero bit
                							P_OneVariable1 = 2'b10,   // the flute should be generated in the one bit
                              P_OneVariable2 = 2'b11;

// low the power 				 
always @(*)
				if(!FD_CLK128)
						active_flipflop = R_ACTIVE;

assign ValidCLK = FD_CLK128 & active_flipflop;


// the reset signal
assign reset_p = RST_P;

// use the RST_P and Active_P as the reset signal. the aim of using the Active_P signal is to recovery initial state
always @(negedge ValidCLK or posedge reset_p)
begin
				if(reset_p)
				       	begin
										PreData <= 0;
                    CurrentData <= 0;
							 	end			
				else   	begin
				            CurrentData <= R_DATAUNCODE;
								 		PreData <= CurrentData;
							 	end
end

// according the ISO14443A,the first bit should generate the zero flute
always @(PreData or CurrentData) 
begin
						OneFlute = 0;
						ZeroFlute = 0;
				case({CurrentData,PreData})
						P_ZeroVariable:	ZeroFlute = 1;
						P_OneVariable1: OneFlute = 1;
						P_OneVariable2: OneFlute = 1;
				endcase
	
end

assign Test1 = ZeroFlute;
assign Test2 = OneFlute;

// 門控
always @(*)	begin
					if(!CLK)
							GatingValidCLK = ValidCLK;
end

// 下降沿觸發采樣的時鐘信號
always @(negedge CLK or posedge RST_P)	begin
					if(RST_P)
								NoneValidCLK_N <= 0;
					else	NoneValidCLK_N <= ~GatingValidCLK;
end

// 下降沿觸發采樣的ZeroFlute
always @(negedge CLK or posedge RST_P)	begin
					if(RST_P)
								ZeroFlute_N <= 0;
					else	ZeroFlute_N <= ZeroFlute;
end

// 0計數的復位信號
always @(posedge CLK or posedge RST_P)	begin
					if(RST_P)
								reset_counterzero <= 0;
					else	reset_counterzero <= ZeroFlute_N & NoneValidCLK_N;
end

// 下降沿觸發采樣的時鐘信號
always @(negedge CLK or posedge RST_P)	begin
					if(RST_P)
								ValidCLK_N <= 0;
					else	ValidCLK_N <= GatingValidCLK;
end

// 下降沿觸發采樣的ZeroFlute
always @(negedge CLK or posedge RST_P)	begin
					if(RST_P)
								OneFlute_N <= 0;
					else	OneFlute_N <= OneFlute;
end

// 1的計數器復位信號
always @(posedge CLK or posedge RST_P)	begin
					if(RST_P)
								reset_counterone <= 0;
					else	reset_counterone <= OneFlute & ValidCLK_N;
end

assign reset_counter = reset_counterzero | reset_counterone;

always @(negedge CLK or negedge reset_counter)
				if(!reset_counter)
							dff_q1 <= 0;
				else	dff_q1 <= ~(dff_q1 | dff_q4);

always @(negedge dff_q1 or negedge reset_counter)
				if(!reset_counter)
							dff_q2 <= 0;
				else  dff_q2 <= (~dff_q2);
				
always @(negedge dff_q2 or negedge reset_counter)
				if(!reset_counter)
							dff_q3 <= 0;
				else  dff_q3 <= (~dff_q3);
				
always @(negedge dff_q3 or negedge reset_counter)
				if(!reset_counter)
							dff_q4 <= 0;
				else  dff_q4 <= (~dff_q4);
	
// 改進米勒碼輸出有效范圍
always @(posedge 	FD_CLK128 or posedge RST_P)	begin
				if(RST_P)
							OutputValid <= 0;
				else	OutputValid <= R_ACTIVE;
end	
				
always @(posedge CLK)	begin
				if(!reset_counter)
							Pulse <= 1;
				else  Pulse <= dff_q4;
end
        
assign  MC_DATACODE = OutputValid? Pulse : 1;
        
endmodule